Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. - Xiangyu Dong 001; Xiaoxia Wu; Guangyu Sun 003; Yuan Xie 001; Hai Li 001; Yiran Chen 001 (DAC, 2008)

System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs). - Xiangyu Dong 001; Yuan Xie 001 (ASP-DAC, 2009)

A novel architecture of the 3D stacked MRAM L2 cache for CMPs. - Guangyu Sun 003; Xiangyu Dong 001; Yuan Xie 001; Jian Li 059; Yiran Chen 001 (HPCA, 2009)

PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM. - Xiangyu Dong 001; Norman P. Jouppi; Yuan Xie 001 (ICCAD, 2009)

3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis. - Ahmed Al-Maashri; Guangyu Sun 003; Xiangyu Dong 001; Vijay Narayanan; Yuan Xie 001 (ICCD, 2009)

Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. - Xiangyu Dong 001; Naveen Muralimanohar; Norman P. Jouppi; Richard Kaufmann; Yuan Xie 001 (SC, 2009)

3D memory stacking for fast checkpointing/restore applications. - Jing Xie 006; Xiangyu Dong 001; Yuan Xie 001 (3DIC, 2010)

Architectural benefits and design challenges for three-dimensional integrated circuits. - Jing Xie 006; Jishen Zhao; Xiangyu Dong 001; Yuan Xie 001 (APCCAS, 2010)

Energy and performance driven circuit design for emerging phase-change memory. - Dimin Niu; Yibo Chen; Xiangyu Dong 001; Yuan Xie 001 (ASP-DAC, 2010)

Cost-driven 3D integration with interconnect layers. - Xiaoxia Wu; Guangyu Sun 003; Xiangyu Dong 001; Reetuparna Das; Yuan Xie 001; Chita R. Das; Jian Li 059 (DAC, 2010)

Cost-aware three-dimensional (3D) many-core multiprocessor design. - Jishen Zhao; Xiangyu Dong 001; Yuan Xie 001 (DAC, 2010)

Energy- and endurance-aware design of phase change memory caches. - Yongsoo Joo; Dimin Niu; Xiangyu Dong 001; Guangyu Sun 003; Naehyuck Chang; Yuan Xie 001 (DATE, 2010)

Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support. - Xiangyu Dong 001; Yuan Xie 001; Naveen Muralimanohar; Norman P. Jouppi (SC, 2010)

Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs. - Xiangyu Dong 001; Jishen Zhao; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

AdaMS: Adaptive MLC/SLC phase-change memory design for file storage. - Xiangyu Dong 001; Yuan Xie 001 (ASP-DAC, 2011)

Design implications of memristor-based RRAM cross-point structures. - Cong Xu 002; Xiangyu Dong 001; Norman P. Jouppi; Yuan Xie 001 (DATE, 2011)

An energy-efficient 3D CMP design with fine-grained voltage scaling. - Jishen Zhao; Xiangyu Dong 001; Yuan Xie 001 (DATE, 2011)

Energy-efficient multi-level cell phase-change memory system with data encoding. - Jue Wang; Xiangyu Dong 001; Guangyu Sun 003; Dimin Niu; Yuan Xie 001 (ICCD, 2011)

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. - Asit K. Mishra; Xiangyu Dong 001; Guangyu Sun 003; Yuan Xie 001; Narayanan Vijaykrishnan; Chita R. Das (ISCA, 2011)

Three-dimensional Integrated Circuits: Design, EDA, and Architecture. - Guangyu Sun 003; Yibo Chen; Xiangyu Dong 001; Jin Ouyang; Yuan Xie 001 (Found. Trends Electron. Des. Autom., 2011)

Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation. - Xiangyu Dong 001; Xiaoxia Wu; Yuan Xie 001; Yiran Chen 001; Hai (Helen) Li (IET Comput. Digit. Tech., 2011)

Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. - Xiangyu Dong 001; Yuan Xie 001; Naveen Muralimanohar; Norman P. Jouppi (ACM Trans. Archit. Code Optim., 2011)

Influence of Stacked 3D Memory/Cache Architectures on GPUs. - Ahmed Al-Maashri; Guangyu Sun 003; Xiangyu Dong 001; Yuan Xie 001; Narayanan Vijaykrishnan (3D Integration for NoC-based SoC Architectures, 2011)

Point and discard: a hard-error-tolerant architecture for non-volatile last level caches. - Jue Wang; Xiangyu Dong 001; Yuan Xie 001 (DAC, 2012)

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. - Xiangyu Dong 001; Cong Xu 002; Yuan Xie 001; Norman P. Jouppi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

OAP: an obstruction-aware cache management policy for STT-RAM last-level caches. - Jue Wang; Xiangyu Dong 001; Yuan Xie 001 (DATE, 2013)

i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations. - Jue Wang; Xiangyu Dong 001; Yuan Xie 001; Norman P. Jouppi (HPCA, 2013)

Low-current probabilistic writes for power-efficient STT-RAM caches. - Nikolaos Strikos; Vasileios Kontorinis; Xiangyu Dong 001; Houman Homayoun; Dean M. Tullsen (ICCD, 2013)

A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies. - Xiangyu Dong 001; Norman P. Jouppi; Yuan Xie 001 (ISPASS, 2013)

A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies. - Xiangyu Dong 001; Norman P. Jouppi; Yuan Xie 001 (ACM Trans. Archit. Code Optim., 2013)

Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing. - Ping Chi; Cong Xu 002; Tao Zhang 032; Xiangyu Dong 001; Yuan Xie 001 (ICCAD, 2014)

ProactiveDRAM: A DRAM-initiated retention management scheme. - Jue Wang; Xiangyu Dong 001; Yuan Xie 001 (ICCD, 2014)

Enabling high-performance LPDDRx-compatible MRAM. - Jue Wang; Xiangyu Dong 001; Yuan Xie 001 (ISLPED, 2014)

Preventing STT-RAM Last-Level Caches from Port Obstruction. - Jue Wang; Xiangyu Dong 001; Yuan Xie 001 (ACM Trans. Archit. Code Optim., 2014)

Building and Optimizing MRAM-Based Commodity Memories. - Jue Wang; Xiangyu Dong 001; Yuan Xie 001 (ACM Trans. Archit. Code Optim., 2014)

Endurance-aware cache line management for non-volatile caches. - Jue Wang; Xiangyu Dong 001; Yuan Xie 001; Norman P. Jouppi (ACM Trans. Archit. Code Optim., 2014)