A 16-GB/S 0-DB Power Back-Off 16-QAM Transmitter at 28 GHZ in 65-NM CMOS. - Xiangyu Meng 003; Can Wang 009; Milad Kalantari; C. Patrick Yue (VLSI Circuits, 2018)

A 28-GHz Compact SPDT Switch Using LC-Based Spiral Transmission Lines in 65-nm CMOS. - Xiangyu Meng 003; Zhenpeng Zheng; Jiaqi Zhang; C. Patrick Yue (A-SSCC, 2019)

A Fully Integrated 150-GHz Transceiver Front-End in 65-nm CMOS. - Xiangyu Meng 003; Baoyong Chi; Yibo Liu; Taikun Ma; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

W-Band Synthesized Modulator and Demodulator with Wideband Performance in 65-nm CMOS. - Zhenpeng Zheng; Xiangyu Meng 003; Jiaqi Zhang; Mo Zhou; Dihu Chen (ISCAS, 2020)

A 0.5-5 GHz 0.3-mW 50% duty-cycle corrector in 65-nm CMOS. - Jiaqi Zhang; Xiangyu Meng 003 (TENCON, 2020)

A 28-GHz 16-Gb/s High Efficiency 16-QAM Transmitter in 65-nm CMOS. - Xiangyu Meng 003; Milad Kalantari; Baoyong Chi; Wenhua Chen 002; Zhijian Chen; Xiaoling Lin; C. Patrick Yue (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA. - Huipeng Deng; Jian Wang 080; Huafeng Ye; Shanlin Xiao; Xiangyu Meng 003; Zhiyi Yu (FCCM, 2021)

A 1.8-GS/s 6-Bit Two-Step SAR ADC in 65-nm CMOS. - Xiangyu Meng 003; Weihao Kong; Haifeng Yang; Yecong Li; Xuan Li (ISCAS, 2021)

Dimension fusion: Dimension-level dynamically composable accelerator for convolutional neural networks. - Huipeng Deng; Jian Wang 080; Huafeng Ye; Shanlin Xiao; Xiangyu Meng 003; Zhiyi Yu (IEICE Electron. Express, 2021)

A 0.2-7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers. - Xiangyu Meng 003; Wang Xie; Jiaqi Zhang; Zhao Zhang 004 (IEEE Trans. Instrum. Meas., 2023)

A V-Band Low-Phase-Noise VCO with Transformer-Based Gm-Boosting Technique. - Biao Wang; Xiangyu Meng 003; Fangfei Ming (ISCAS, 2024)

A 3.3-V Ku-Band Front-End Module With 2.6-dB NF and 18.9-dBm OP1dB in 65-nm CMOS. - Ting Huang; Xiangyu Meng 003; Gaoyuan Zhao; Baoyong Chi (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Sample-and-Hold-Based 453-ps True Time Delay Circuit With a Wide Bandwidth of 0.5-2.5 GHz in 65-nm CMOS. - Chuanjie Chen; Xiangyu Meng 003; Wang Xie; Baoyong Chi (IEEE Trans. Very Large Scale Integr. Syst., 2025)