Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction. - Yuki Fujita; Fengwei An; Aiwen Luo; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (APCCAS, 2016)

Dynamically reconfigurable system for LVQ-based on-chip learning and recognition. - Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (ISCAS, 2016)

A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration. - Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (IEEE Trans. Multi Scale Comput. Syst., 2016)

Object-recognition VLSI for pedestrian detection in automotive applications. - Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Idaku Ishii (ASICON, 2017)

A Vector-Quantization Compression Circuit With On-Chip Learning Ability for High-Speed Image Sensor. - Zunkai Huang; Xiangyu Zhang 002; Lei Chen 001; Yongxin Zhu 001; Fengwei An; Hui Wang 036; Songlin Feng (IEEE Access, 2017)

Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures. - Jungang Guan; Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (Sensors, 2017)

A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization. - Xiangyu Zhang 002; Fengwei An; Lei Chen 001; Idaku Ishii; Hans Jürgen Mattausch (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space. - Fengwei An; Xiangyu Zhang 002; Aiwen Luo; Lei Chen 001; Hans Jürgen Mattausch (IEEE Trans. Circuits Syst. Video Technol., 2018)

Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS. - Aiwen Luo; Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier. - Aiwen Luo; Fengwei An; Xiangyu Zhang 002; Hans Jürgen Mattausch (IEEE Access, 2019)

Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm. - Jungang Guan; Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (IEICE Trans. Inf. Syst., 2019)

Motion Assisted Video-based Stereo Matching. - Shengyu Gao; Hongyu Wang 010; Teng Wang; Yang Wang; Xiangyu Zhang 002; Xin Lou (APCCAS, 2021)

Robust Multi-Source Direction of Arrival Estimation Using a Single Acoustic Vector Sensor. - Jianhua Geng; Sifan Wang; Juan Li; Jingwei Li; Xiangyu Zhang 002; Xin Lou (APCCAS, 2021)

Stereo Point Cloud Refinement for 3D Object Detection. - Wangchao Liu; Teng Wang; Yang Wang; Xiangyu Zhang 002; Xin Lou (APCCAS, 2021)

Spatial Non-Maximum Suppression for Object Detection using Correlation and Dynamic Thresholds. - Xiangyu Zhang 002; Wenyan Su; Juan Li; Jingwei Li; Xin Lou (ISOCC, 2021)

FPGA Accelerator for Radar-Based Human Activity Recognition. - Kangjie Long; Chaolin Rao; Xiangyu Zhang 002; Wen Bin Ye 001; Xin Lou (AICAS, 2022)

A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGA. - Hongyu Wang 010; Wei Zhou 037; Xiangyu Zhang 002; Xin Lou (CICC, 2022)

An End-to-end Computer Vision System Architecture. - Ling Zhang 010; Wei Zhou 037; Xiangyu Zhang 002; Xin Lou (ISCAS, 2022)

A Block PatchMatch-Based Energy-Resource Efficient Stereo Matching Processor on FPGA. - Hongyu Wang 010; Wei Zhou 037; Xiangyu Zhang 002; Xin Lou (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Raw Image-Based End-to-End Object Detection Accelerator Using HOG Features. - Xiangyu Zhang 002; Ling Zhang 010; Xin Lou (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Image Frequency Separation Residual Network for End-to-end RAW to RGB Mapping. - Mengchuan Dong; Wei Zhou 037; Cong Pang; Xiangyu Zhang 002; Xin Lou (AICAS, 2023)

An Efficient Frequency Domain Vision Pipeline From RAW Images to Backend Tasks. - Haoyan Li; Wei Zhou 037; Xiangyu Zhang 002; Xin Lou (ISCAS, 2023)

A Multi-scale Block PatchMatch-based Unified Algorithm for Efficient 6-D Vision Processing. - Hongyu Wang 010; Xiangyu Zhang 002; Xin Lou (ISCAS, 2024)

FPGA Accelerator for Human Activity Recognition Based on Radar. - Kangjie Long; Chaolin Rao; Xiangyu Zhang 002; Wenbin Ye 001; Xin Lou (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

RAW Images-Based Motion-Assisted Object Detection Accelerator Using Deformable Parts Models Features on 1080p Videos. - Ling Zhang 010; Haoyan Li; Xiangyu Zhang 002; Xin Lou (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)