NISD: A Framework for Automatic Narrow Instruction Set Design. - Xianhua Liu 001; Jiyu Zhang; Xu Cheng 001 (ICESS, 2007)

Efficient code size reduction without performance loss. - Xianhua Liu 001; Jiyu Zhang; Xu Cheng 001 (SAC, 2007)

Bit-level optimization for high-level synthesis and FPGA-based acceleration. - Jiyu Zhang; Zhiru Zhang; Sheng Zhou; Mingxing Tan; Xianhua Liu 001; Xu Cheng 001; Jason Cong (FPGA, 2010)

Research Progress of UniCore CPUs and PKUnity SoCs. - Xu Cheng 001; Xiaoyin Wang; Junlin Lu; Jiangfang Yi; Dong Tong 001; Xuetao Guan; Feng Liu; Xianhua Liu 001; Chun Yang; Yi Feng 003 (J. Comput. Sci. Technol., 2010)

Energy-efficient branch prediction with Compiler-guided History Stack. - Mingxing Tan; Xianhua Liu 001; Zichao Xie; Dong Tong 001; Xu Cheng 001 (DATE, 2012)

CVP: an energy-efficient indirect branch prediction with compiler-guided value pattern. - Mingxing Tan; Xianhua Liu 001; Tong Tong; Xu Cheng 001 (ICS, 2012)

Exploration of the Relationship Between Just-in-Time Compilation Policy and Number of Cores. - Mingkai Huang; Xianhua Liu 001; Tingyu Zhang; Xu Cheng 001 (ICA3PP (4), 2015)

An Energy-Efficient Branch Prediction with Grouped Global History. - Mingkai Huang; Dan He; Xianhua Liu 001; Mingxing Tan; Xu Cheng 001 (ICPP, 2015)

MFAP: Fair Allocation between fully backlogged and non-fully backlogged applications. - Yan Sui; Chun Yang; Dong Tong 001; Xianhua Liu 001; Xu Cheng 001 (ICCD, 2016)

Content Look-Aside Buffer for Redundancy-Free Virtual Disk I/O and Caching. - Chun Yang; Xianhua Liu 001; Xu Cheng 001 (VEE, 2017)

An Efficient Register Renaming Technique with Delayed Allocation and Register Packing. - Xianhua Liu 001; Qinghong Yang; Miao Tao; Qinshu Chen; Xu Cheng 001 (ICECS, 2020)

Efficient arithmetic expression optimization with weighted adjoint matrix. - Xianhua Liu 001; Chun Yang; Zixin Guan (IPCCC, 2020)

FTCLNet: Convolutional LSTM with Fourier Transform for Vulnerability Detection. - Defu Cao; Jing Huang; Xuanyu Zhang; Xianhua Liu 001 (TrustCom, 2020)

MBAPIS: Multi-Level Behavior Analysis Guided Program Interval Selection for Microarchitecture Studies. - Hongwei Cui; Yujie Cui; Honglan Zhan; Shuhao Liang; Xianhua Liu 001; Chun Yang; Xu Cheng 001 (PACT, 2023)

A Hardware-Software Cooperative Interval-Replaying for FPGA-based Architecture Evaluation. - Hongwei Cui; Shuhao Liang; Yujie Cui; Weiqi Zhang; Honglan Zhan; Chun Yang; Xianhua Liu 001; Xu Cheng 001 (DATE, 2023)

High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port Operation. - Honglan Zhan; Chenxi Wang; Hongwei Cui; Xianhua Liu 001; Feng Liu; Xu Cheng 001 (DATE, 2023)

Multi: Reduce Energy Overhead of Criticality-Aware Dynamic Instruction Scheduling for Energy Efficiency. - Honglan Zhan; Chenxi Wang; Xin Wang; Chun Yang; Xianhua Liu 001; Xu Cheng 001 (ICCD, 2024)