Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory. - Shouyi Yin; Xianqing Yao; Tianyi Lu; Leibo Liu; Shaojun Wei (ICCAD, 2016)

Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures. - Shouyi Yin; Xianqing Yao; Dajiang Liu; Leibo Liu; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). - Tianyi Lu; Shouyi Yin; Xianqing Yao; Zhicong Xie; Leibo Liu; Shaojun Wei (FPGA, 2017)

Memory fartitioning-based modulo scheduling for high-level synthesis. - Tianyi Lu; Shouyi Yin; Xianqing Yao; Zhicong Xie; Leibo Liu; Shaojun Wei (ISCAS, 2017)

Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory. - Shouyi Yin; Xianqing Yao; Tianyi Lu; Dajiang Liu; Jiangyuan Gu; Leibo Liu; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2017)

Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis. - Shouyi Yin; Tianyi Lu; Xianqing Yao; Zhicong Xie; Leibo Liu; Shaojun Wei (IEEE Access, 2018)