Xiao Liu

Affiliations:
  • University of California, Berkeley, CA, USA
  • Chinese University of Hong Kong, Department of Computer Science and Engineering, Hong Kong (former)


According to our database1, Xiao Liu authored at least 21 papers between 2008 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Trace-Based Post-Silicon Validation for VLSI Circuits
Lecture Notes in Electrical Engineering 252, Springer, ISBN: 978-3-319-00532-4, 2014

2013
On Multiplexed Signal Tracing for Post-Silicon Validation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2012
On X-Variable Filling and Flipping for Capture-Power Reduction in Linear Decompressor-Based Test Compression Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon Validation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

On efficient silicon debug with flexible trace interconnection fabric.
Proceedings of the 2012 IEEE International Test Conference, 2012

X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Capture-power-aware test data compression using selective encoding.
Integr., 2011

Pseudo-functional testing for small delay defects considering power supply noise effects.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

On High-Quality Test Pattern Selection and Manipulation.
Proceedings of the 16th European Test Symposium, 2011

On multiplexed signal tracing for post-silicon debug.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects.
Proceedings of the Design, Automation and Test in Europe, 2010

On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

On signal tracing in post-silicon validation.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Trace signal selection for debugging electrical errors in post-silicon validation.
Proceedings of the 2009 IEEE International Test Conference, 2009

On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment.
Proceedings of the 2009 IEEE International Test Conference, 2009

A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment.
Proceedings of the Design, Automation and Test in Europe, 2009

Trace signal selection for visibility enhancement in post-silicon validation.
Proceedings of the Design, Automation and Test in Europe, 2009

Interconnection fabric design for tracing signals in post-silicon validation.
Proceedings of the 46th Design Automation Conference, 2009

2008
A Generic Framework for Scan Capture Power Reduction in Test Compression Environment.
Proceedings of the 2008 IEEE International Test Conference, 2008

On capture power-aware test data compression for scan-based testing.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

On Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon Validation.
Proceedings of the 17th IEEE Asian Test Symposium, 2008


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