High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder. - Xiao Peng 002; Zhixiang Chen 002; Xiongxin Zhao; Fumiaki Maehara; Satoshi Goto (ASAP, 2010)

An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards. - Zhixiang Chen 002; Xiongxin Zhao; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (ISCAS, 2010)

Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network. - Xiao Peng 002; Zhixiang Chen 002; Xiongxin Zhao; Fumiaki Maehara; Satoshi Goto (IEICE Trans. Electron., 2010)

Generic Permutation Network for QC-LDPC Decoder. - Xiao Peng 002; Xiongxin Zhao; Zhixiang Chen 002; Fumiaki Maehara; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application. - Zhixiang Chen 002; Xiongxin Zhao; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

High-parallel LDPC decoder with power gating design. - Ying Cui; Xiao Peng 002; Yu Jin; Peilin Liu; Shinji Kimura; Satoshi Goto (ASICON, 2011)

A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS. - Xiao Peng 002; Zhixiang Chen 002; Xiongxin Zhao; Dajiang Zhou; Satoshi Goto (A-SSCC, 2011)

A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering. - Qian Xie; Qian He; Xiao Peng 002; Ying Cui; Zhixiang Chen 002; Dajiang Zhou; Satoshi Goto (SiPS, 2011)

Ultra low power QC-LDPC decoder with high parallelism. - Ying Cui; Xiao Peng 002; Zhixiang Chen 002; Xiongxin Zhao; Yichao Lu; Dajiang Zhou; Satoshi Goto (SoCC, 2011)

A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip. - Zhixiang Chen 002; Xiao Peng 002; Xiongxin Zhao; Leona Okamura; Dajiang Zhou; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Distributed punctured LDPC coding scheme using novel shuffled decoding for MIMO relay channels. - Nanfan Qiu; Xiao Peng 002; Yichao Lu; Satoshi Goto (EUSIPCO, 2012)

De-blocking Filter Design for HEVC and H.264/AVC. - Muchen Li; Jinjia Zhou; Dajiang Zhou; Xiao Peng 002; Satoshi Goto (PCM, 2012)

A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX. - Xiongxin Zhao; Xiao Peng 002; Zhixiang Chen 002; Dajiang Zhou; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

DVB-T2 LDPC Decoder with Perfect Conflict Resolution. - Xiongxin Zhao; Zhixiang Chen 002; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS. - Zhixiang Chen 002; Xiao Peng 002; Xiongxin Zhao; Leona Okamura; Dajiang Zhou; Satoshi Goto (ASP-DAC, 2013)

High-parallel performance-aware LDPC decoder IP core design for WiMAX. - Xiongxin Zhao; Zhixiang Chen 002; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (MWSCAS, 2013)

A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC. - Muchen Li; Jinjia Zhou; Dajiang Zhou; Xiao Peng 002; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS. - Xiongxin Zhao; Zhixiang Chen 002; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Dynamic Check Message Majority-Logic Decoding Algorithm for Non-binary LDPC Codes. - Yichao Lu; Xiao Peng 002; Guifen Tian; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)