A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs. - Xiao Wang 021; Fule Li; Zhihua Wang 001 (ISCAS, 2016)

A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique. - Chengwei Wang; Xiao Wang 021; Yang Ding; Fule Li; Zhihua Wang 001 (ISCAS, 2018)

A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process. - Xiao Wang 021; Chengwei Wang; Fule Li; Zhihua Wang 001 (ISCAS, 2018)

A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration. - Xiao Wang 021; Fule Li; Wen Jia; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique. - Meng Ni; Xiao Wang 021; Zhe Zhou; Yang Ding; Fule Li; Woogeun Rhee; Zhihua Wang 001 (MWSCAS, 2020)

A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC. - Meng Ni; Xiao Wang 021; Zhe Zhou; Yang Ding; Fule Li; Woogeun Rhee; Zhihua Wang 001 (MWSCAS, 2020)

A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs. - Xiao Wang 021; Fule Li; Zhihua Wang 001 (IEEE Trans. Circuits Syst., 2020)

A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction. - Peilin Yang; Xiao Wang 021; Chengwei Wang; Fule Li; Hanjun Jiang; Zhihua Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation. - Meng Ni; Xiao Wang 021; Fule Li; Zhihua Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy. - Meng Ni; Xiao Wang 021; Fule Li; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)