Benchmark of RRAM based Architectures for Dot-Product Computation. - Xiaochen Peng; Shimeng Yu (APCCAS, 2018)

Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. - Xiaoyu Sun 001; Xiaochen Peng; Pai-Yu Chen; Rui Liu 005; Jae-sun Seo; Shimeng Yu (ASP-DAC, 2018)

Parallelizing SRAM arrays with customized bit-cell for binary neural networks. - Rui Liu 005; Xiaochen Peng; Xiaoyu Sun 001; Win-San Khwa; Xin Si; Jia-Jing Chen; Jia-Fang Li; Meng-Fan Chang; Shimeng Yu (DAC, 2018)

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. - Xiaoyu Sun 001; Shihui Yin; Xiaochen Peng; Rui Liu 005; Jae-sun Seo; Shimeng Yu (DATE, 2018)

Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing. - Jiyong Woo; Xiaochen Peng; Shimeng Yu (ISCAS, 2018)

A Versatile ReRAM-based Accelerator for Convolutional Neural Networks. - Manqing Mao; Xiaoyu Sun 001; Xiaochen Peng; Shimeng Yu; Chaitali Chakrabarti (SiPS, 2018)

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. - Pai-Yu Chen; Xiaochen Peng; Shimeng Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design. - Rui Liu 005; Pai-Yu Chen; Xiaochen Peng; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis. - Wenqiang Zhang; Xiaochen Peng; Huaqiang Wu; Bin Gao 006; Hu He 001; Youhui Zhang; Shimeng Yu; He Qian (DAC, 2019)

MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm Optimizations. - Yandong Luo; Xiaochen Peng; Shimeng Yu (ICONS, 2019)

Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture. - Xiaochen Peng; Rui Liu 005; Shimeng Yu (ISCAS, 2019)

CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training. - Hongwu Jiang; Xiaochen Peng; Shanshi Huang; Shimeng Yu (MEMSYS, 2019)

Inference engine benchmarking across technological platforms from CMOS to RRAM. - Xiaochen Peng; Minkyu Kim 001; Xiaoyu Sun 001; Shihui Yin; Titash Rakshit; Ryan M. Hatcher; Jorge A. Kittl; Jae-sun Seo; Shimeng Yu (MEMSYS, 2019)

MAX2: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization. - Manqing Mao; Xiaochen Peng; Rui Liu 005; Jingtao Li; Shimeng Yu; Chaitali Chakrabarti (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects. - Shimeng Yu; Xiaoyu Sun 001; Xiaochen Peng; Shanshi Huang (CICC, 2020)

A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. - Hongwu Jiang; Shanshi Huang; Xiaochen Peng; Jian-Wei Su; Yen-Chi Chou; Wei-Hsing Huang; Ta-Wei Liu; Ruhui Liu; Meng-Fan Chang; Shimeng Yu (DAC, 2020)

Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories. - Shanshi Huang; Xiaoyu Sun 001; Xiaochen Peng; Hongwu Jiang; Shimeng Yu (DATE, 2020)

XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption. - Shanshi Huang; Hongwu Jiang; Xiaochen Peng; Wantong Li; Shimeng Yu (ICCAD, 2020)

MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture. - Hongwu Jiang; Shanshi Huang; Xiaochen Peng; Shimeng Yu (ISCAS, 2020)

A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out. - Yandong Luo; Xiaochen Peng; Ryan Hatcher; Titash Rakshit; Jorge Kittl; Mark S. Rodder; Jae-Sun Seo; Shimeng Yu (ISCAS, 2020)

Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine. - Wonbo Shim; Hongwu Jiang; Xiaochen Peng; Shimeng Yu (MEMSYS, 2020)

CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays. - Hongwu Jiang; Xiaochen Peng; Shanshi Huang; Shimeng Yu (IEEE Trans. Computers, 2020)

Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures. - Xiaochen Peng; Rui Liu 005; Shimeng Yu (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint. - Anni Lu; Xiaochen Peng; Yandong Luo; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance. - Ankit Kaul; Yandong Luo; Xiaochen Peng; Shimeng Yu; Muhannad S. Bakir (3DIC, 2021)

NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro. - Anni Lu; Xiaochen Peng; Wantong Li; Hongwu Jiang; Shimeng Yu (AICAS, 2021)

Compute-in-RRAM with Limited On-chip Resources. - Anni Lu; Xiaochen Peng; Shimeng Yu (AICAS, 2021)

A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator. - Anni Lu; Xiaochen Peng; Yandong Luo; Shanshi Huang; Shimeng Yu (DATE, 2021)

Compute-in-Memory: From Device Innovation to 3D System Integration. - Shimeng Yu; Wonbo Shim; Jae Hur; Yuan-chun Luo; Gihun Choe; Wantong Li; Anni Lu; Xiaochen Peng (ESSDERC, 2021)

Impact of Multilevel Retention Characteristics on RRAM based DNN Inference Engine. - Wonbo Shim; Jian Meng; Xiaochen Peng; Jae-sun Seo; Shimeng Yu (IRPS, 2021)

Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning. - Shanshi Huang; Xiaochen Peng; Hongwu Jiang; Yandong Luo; Shimeng Yu (ISCAS, 2021)

Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator. - Panni Wang; Xiaochen Peng; Wriddhi Chakraborty; Asif Khan; Suman Datta; Shimeng Yu (ISCAS, 2021)

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark. - Anni Lu; Xiaochen Peng; Wantong Li; Hongwu Jiang; Shimeng Yu (Frontiers Artif. Intell., 2021)

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training. - Xiaochen Peng; Shanshi Huang; Hongwu Jiang; Anni Lu; Shimeng Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

RRAM for Compute-in-Memory: From Inference to Training. - Shimeng Yu; Wonbo Shim; Xiaochen Peng; Yandong Luo (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks. - Jian Meng; Li Yang 009; Xiaochen Peng; Shimeng Yu; Deliang Fan; Jae-Sun Seo (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference. - Anni Lu; Xiaochen Peng; Yandong Luo; Shanshi Huang; Shimeng Yu (ACM Trans. Design Autom. Electr. Syst., 2021)

Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption. - Shanshi Huang; Hongwu Jiang; Xiaochen Peng; Wantong Li; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices. - Shanshi Huang; Xiaoyu Sun 001; Xiaochen Peng; Hongwu Jiang; Shimeng Yu (ACM Trans. Design Autom. Electr. Syst., 2022)

Benchmark Framework for 2-D/3-D Integrated Compute-in-Memory Based Machine Learning Accelerator. - Xiaochen Peng (2022)

Non-volatile Memory Technologies for Edge AI Applications. - Xiaoyu Sun 001; Win-San Khwa; Xiaochen Peng; Meng-Fan Chang; Kerem Akarvardar (ICCAD, 2024)

34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. - Hidehiro Fujiwara; Haruki Mori; Wei-Chang Zhao; Kinshuk Khare; Cheng-En Lee; Xiaochen Peng; Vineet Joshi; Chao-Kai Chuang; Shu-Huan Hsu; Takeshi Hashizume; Toshiaki Naganuma; Chen-Hung Tien; et al. (ISSCC, 2024)

Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators. - Ankit Kaul; Madison Manley; James Read; Yandong Luo; Xiaochen Peng; Shimeng Yu; Muhannad S. Bakir (VLSI Technology and Circuits, 2024)

Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework. - Xiaoyu Sun 001; Xiaochen Peng; Sai Qian Zhang; Jorge Gomez 002; Win-San Khwa; Syed Shakib Sarwar; Ziyun Li; Weidong Cao 001; Zhao Wang; Chiao Liu; Meng-Fan Chang; Barbara De Salvo; et al. (ACM Trans. Design Autom. Electr. Syst., 2024)