Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology. - Xiaofeng Yang 004; Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A -246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT. - Xiaofeng Yang 004; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (ISSCC, 2019)

A Calibration-Free Ring-Oscillator PLL With Gain Tracking Achieving 9% Jitter Variation Over PVT. - Xiaofeng Yang 004; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

A 0.016mm2 Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling. - Junlin Zhong; Xiaofeng Yang 004; Rui Paulo Martins; Yan Zhu 001; Chi-Hang Chan (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Topkima-Former: Low-Energy, Low-Latency Inference for Transformers Using Top-k In-Memory ADC. - Shuai Dong; Junyi Yang; Xiaoqi Peng; Hongyang Shang; Ye Ke; Xiaofeng Yang 004; Hongjie Liu; Arindam Basu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)