High Speed Multi-channel Data Cache Design Based on DDR3 SDRAM. - Xiaofeng Yang 006; Ancheng Liu; Jinjin Wang (AIPR, 2022)

Design and Implementation of Miniaturized Flight Control Computer Based on FPGA+DSP. - Xiaofeng Yang 006; Chaochao Qiu (AIPR, 2022)

Design of Communication Controller Chip Based on FlexRay Bus. - Xiaofeng Yang 006; Yaling Su (AIPR, 2022)

Bad Block Detection of Spaceborne NAND Flash Based on FPGA. - Xiaofeng Yang 006; Jinjin Wang; Ancheng Liu (AIPR, 2022)

Design and verification of SRAM controller based on FPGA. - Xiaofeng Yang 006; Gulin Chen (AIPR, 2023)

Research on Spaceborne Memory Control Based on FPGA Configuration Refresh Technology. - Xiaofeng Yang 006; Chuang Wu (AIPR, 2023)

Design of High Performance Dynamic DMA Based on Multidimensional Nesting Technology. - Xin Li; Xiaofeng Yang 006 (AIPR, 2023)

Design of 18-25GHz On-chip Double-balanced Passive Mixer. - Xiaofeng Yang 006; Pingyan Dong (AIPR, 2023)

Design and Verification of a High Performance Deserial Serial Peripheral Interface. - Xiaofeng Yang 006; Yongnian Jiang; Mingxi Ren (AIPR, 2023)