FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes. - Xiaoheng Chen; Qin Huang 002; Shu Lin 001; Venkatesh Akella (Allerton, 2009)

Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing. - Xiaoheng Chen; Jingyu Kang; Shu Lin 001; Venkatesh Akella (DATE, 2009)

QSN - A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders. - Xiaoheng Chen; Shu Lin 001; Venkatesh Akella (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders. - Xiaoheng Chen; Jingyu Kang; Shu Lin 001; Venkatesh Akella (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes. - Xiaoheng Chen; Jingyu Kang; Shu Lin 001; Venkatesh Akella (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA. - Xiaoheng Chen; Venkatesh Akella (ACM Trans. Reconfigurable Technol. Syst., 2011)

Exploiting the shift property of structured LDPC codes for reduced-complexity sliced message passing based decoder design. - Xiaoheng Chen; Chung-Li Wang (ICNC, 2012)

Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes. - Xiaoheng Chen; Shu Lin 001; Venkatesh Akella (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm. - Xiaoheng Chen; Chung-Li Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes. - Chung-Li Wang; Xiaoheng Chen; Zongwang Li; Shaohua Yang (IEEE Trans. Commun., 2013)