Semi-Hiding Operators and the Analysis of Active-Edge Specifications for Digital Circuits. - Radu Negulescu; Xiaohua Kong (ACSD, 2001)

Formal verification of pulse-mode asynchronous circuits. - Xiaohua Kong; Radu Negulescu (ASP-DAC, 2001)

Refinement-Based Formal Verification of Asynchronous Wrappers for Independently Clocked Domains in Systems on Chip. - Xiaohua Kong; Radu Negulescu; Larry Weidong Ying (CHARME, 2001)

Formal Verification of Peephole Optimizations in Asynchronous Circuits. - Xiaohua Kong; Radu Negulescu (FORTE, 2001)

Refinement-based formal verification with heterogeneous timing. - Xiaohua Kong; Radu Negulescu; Larry Weidong Ying (Int. J. Softw. Tools Technol. Transf., 2003)

Bolstering Faith in GasP Circuits through Formal Verification. - Xiaohua Kong; Radu Negulescu (ASYNC, 2004)

High-Speed Reduced Stack Dual Lock Circuits. - Nisrine Saadallah; Xiaohua Kong; Radu Negulescu (ASYNC, 2004)

Semihiding operators and active-edge specification. - Xiaohua Kong; Radu Negulescu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network. - Amirali Shayan Arani; Xiang Hu; He Peng; Wenjian Yu; Wanping Zhang; Chung-Kuan Cheng; Mikhail Popovich; Xiaoming Chen; Lew Chua-Eoan; Xiaohua Kong (ISQED, 2009)

Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond. - Alvin Leng Sun Loke; Da Yang 007; Tin Tin Wee; Jonathan L. Holland; Patrick Isakanian; Kern Rim; Sam Yang; Jacob S. Schneider; Giri Nallapati; Sreeker Dundigal; Hasnain Lakdawala; Behnam Amelifard; et al. (CICC, 2019)