A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail. - Xiaohui Lin 012; Mohamed Megahed; Tejasvi Anand (VLSI Technology and Circuits, 2022)

Minimum Power Point Design of Inverter Based Continuous Time Linear Equalizer (CTLE). - Andrew Ensinger; Ramin Javadi; Xiaohui Lin 012; Bella Bose; Tejasvi Anand (ISCAS, 2024)