Modeling and Classification of sEMG Based on Blind Identification Theory. - Yang Li; Yantao Tian; Xiaojing Shang; Wanzhong Chen (ISNN (3), 2011)

Modeling and Classification of sEMG Based on Instrumental Variable Identification. - Xiaojing Shang; Yantao Tian; Yang Li (ISNN (3), 2011)

RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism. - Xiaojing Shang; Ming Ling; Shan Shen; Tianxiang Shao; Jun Yang 006 (MEMSYS, 2019)

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM. - Ming Ling; Xiaojing Shang; Shan Shen; Tianxiang Shao; Jun Yang 006 (IEEE Access, 2019)

Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations. - Ming Ling; Xiaojing Shang; Kecheng Ji; Longxing Shi (Microprocess. Microsystems, 2019)

TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages. - Shan Shen; Tianxiang Shao; Xiaojing Shang; Yichen Guo; Ming Ling; Jun Yang 006; Longxing Shi (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Augmented reality in vocational training: A systematic review of research and applications. - Feng-Kuang Chiang; Xiaojing Shang; Lu Qiao (Comput. Hum. Behav., 2022)