Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm. - Xiaoxin Cui; Dunshan Yu; Shimin Sheng; Xiaole Cui (APCCAS, 2006)

Towards HMM based human motion recognition using MEMS inertial sensors. - Guangyi Shi; Yuexian Zou; Yufeng Jin; Xiaole Cui; Wen Jung Li (ROBIO, 2008)

Modeling and testing of interference faults in the nano NAND Flash memory. - Jin Zha; Xiaole Cui; Chung Len Lee 001 (DATE, 2012)

A novel test scheme for NAND flash memory based on built-in oscillator ring. - Si Chen; Xiaole Cui; Chung Len Lee 001 (ASICON, 2013)

AHardware implementation of DES with combined countermeasure against DPA. - Xiaoxin Cui; Rui Li; Wei Wei; Juan Gu; Xiaole Cui (ASICON, 2013)

New DfT architectures for 3D-SICs with a wireless test port. - Yibo He; Xiaole Cui; Chung Len Lee 001; Xiaoxin Cui; Yufeng Jin (ASICON, 2013)

Enhanced error correction against multiple-bit-upset based on BCH code for SRAM. - Weijia Ma; Xiaole Cui; Chung Len Lee 001 (ASICON, 2013)

A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications. - Zhengyu Qian; Xiaole Cui; Bo Wang 016; Xiangrong Zhang; Chung Len Lee 001 (ASICON, 2013)

A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique. - Xuan Yang; Xiaole Cui; Chao Wang; Chung Len Lee 001 (ASICON, 2013)

A UWB mixer with a balanced wide band active balun using crossing centertaped inductor. - Xiangrong Zhang; Xiaole Cui; Bo Wang 016; Chung Len Lee 001 (ISCAS, 2013)

Post-bond test for TSVs using voltage division. - Bingqiang Jing; Xiaole Cui; Yalin Ran; Yufeng Jin (ASICON, 2015)

A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications. - Nan Liao; Xiaoxin Cui; Tian Wang; Kai Liao; Yewen Ni; Dunshan Yu; Xiaole Cui (ASICON, 2015)

A countermeasure for power analysis to scalar multiplication of ECC hardware. - Lifei Liu; Xiaole Cui; Yalin Ran; Xiaoxin Cui (ASICON, 2015)

Employing the mixed FBB/RBB in the design of FinFET logic gates. - Tian Wang; Xiaoxin Cui; Kai Liao; Nan Liao; Yewen Ni; Dunshan Yu; Xiaole Cui (ASICON, 2015)

An enhanced decoder for multiple-bit error correcting BCH codes. - Hupo Wei; Xiaole Cui; Qiang Zhang; Yufeng Jin (ASICON, 2015)

A TSV repair method for clustered faults. - Shijie Zhang; Xiaole Cui; Qiang Zhang; Yufeng Jin (ASICON, 2015)

Context-adaptive fast motion estimation of HEVC. - Xufeng Li; Ronggang Wang; Xiaole Cui; Wenmin Wang 001 (ISCAS, 2015)

Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure. - Zuolin Cheng; Xiaole Cui; Xiaoxin Cui; Chung Len Lee 001 (IET Comput. Digit. Tech., 2015)

A snake addressing scheme for phase change memory testing. - Xiaole Cui; Zuolin Cheng; Chung-Len Lee 001; Xinnan Lin; Yiqun Wei; Xiaogang Chen; Zhitang Song (Sci. China Inf. Sci., 2016)

Ultralow-power high-speed flip-flop based on multimode FinFETs. - Kai Liao; Xiaoxin Cui; Nan Liao; Tian Wang; Dunshan Yu; Xiaole Cui (Sci. China Inf. Sci., 2016)

Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology. - Tian Wang; Xiaoxin Cui; Kai Liao; Nan Liao; Xiaole Cui; Dunshan Yu (IEICE Trans. Electron., 2016)

A practical cold boot attack on RSA private keys. - Tian Wang; Xiaoxin Cui; Yewen Ni; Dunshan Yu; Xiaole Cui; Gang Qu 001 (AsianHOST, 2017)

Design of router for spiking neural networks. - Yewen Ni; Xiaoxin Cui; Yuanning Fan; Qiankun Han; Kefei Liu 002; Xiaole Cui (ASICON, 2017)

Improving DFA on AES using all-fault ciphertexts. - Yewen Ni; Xiaoxin Cui; Tian Wang; Yuanning Fan; Qiankun Han; Kefei Liu 002; Xiaole Cui (ASICON, 2017)

A design of high performance full adder with memristors. - Kuimin Zhang; Xiaole Cui; Xiaoxin Cui (ASICON, 2017)

A signal noise separation method for the instant mixing linear and nonlinear circuits with MISEP algorithm. - Liwen Zhu 002; Xiaole Cui; Xiang Li; Xiaoxin Cui (ASICON, 2017)

A Heuristic Algorithm for Automatic Generation of March Tests. - Xiaole Cui; Yichi Luo; Qiujun Lin; Xiaoxin Cui (ATS, 2017)

A new calibration method for MEMS accelerometers with genetic algorithm. - Xiaole Cui; Chunliang Liu; Guangyi Shi; Yufeng Jin (RCAR, 2017)

Testing of 1TnR RRAM array with sneak path technique. - Xiaole Cui; Qiang Zhang; Xiaoxin Cui; Xin'an Wang; Jinfeng Kang; Xiaoyan Liu (Sci. China Inf. Sci., 2017)

Improving DFA attacks on AES with unknown and random faults. - Nan Liao; Xiaoxin Cui; Kai Liao; Tian Wang; Dunshan Yu; Xiaole Cui (Sci. China Inf. Sci., 2017)

High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ). - Kai Liao; Xiaoxin Cui; Nan Liao; Tian Wang; Dunshan Yu; Xiaole Cui (IEEE Trans. Ind. Electron., 2017)

An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias. - Xiaole Cui; Xiaoxin Cui; Yewen Ni; Min Miao; Yufeng Jin (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Polymorphic gate based IC watermarking techniques. - Tian Wang; Xiaoxin Cui; Dunshan Yu; Omid Aramoon; Timothy Dunlap; Gang Qu 001; Xiaole Cui (ASP-DAC, 2018)

A Novel Polymorphic Gate Based Circuit Fingerprinting Technique. - Tian Wang; Xiaoxin Cui; Dunshan Yu; Omid Aramoon; Timothy Dunlap; Gang Qu 001; Xiaole Cui (ACM Great Lakes Symposium on VLSI, 2018)

Design of Low-Power High-Performance FinFET Standard Cells. - Tian Wang; Xiaoxin Cui; Kai Liao; Nan Liao; Dunshan Yu; Xiaole Cui (Circuits Syst. Signal Process., 2018)

Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits. - Tian Wang; Xiaoxin Cui; Yewen Ni; Dunshan Yu; Xiaole Cui (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Flash-based Computing in-Memory Scheme for IOT. - Jinfeng Kang; Peng Huang 004; Runze Han; Yachen Xiang; Xiaole Cui; Xiaoyan Liu (ASICON, 2019)

Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing. - Runze Han; Peng Huang 004; Yudi Zhao; Xiaole Cui; Xiaoyan Liu; Jinfeng Kang (Sci. China Inf. Sci., 2019)

A Testability Enhancement Method for the Memristor Ratioed Logic Circuits. - Li Qu; Xiaole Cui; Xiaoxin Cui (ATS, 2020)

ReTriple: Reduction of Redundant Rendering on Android Devices for Performance and Energy Optimizations. - Xianfeng Li; Gengchao Li; Xiaole Cui (DAC, 2020)

A synthesis method for logic circuits in RRAM arrays. - Xiaole Cui; Xiao Ma; Feng Wei; Xiaoxin Cui (Sci. China Inf. Sci., 2020)

Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates. - Xiaole Cui; Xiao Ma; Qiujun Lin; Xiang Li; Hang Zhou; Xiaoxin Cui (Circuits Syst. Signal Process., 2020)

The synthesis method of logic circuits based on the iMemComp gates. - Xiaole Cui; Qiujun Lin; Xiaoxin Cui; Feng Wei; Xiaoyan Liu; Jinfeng Kang (Integr., 2020)

The logic obfuscation of LFSR with the crosstalk based polymorphic gate. - Yuqian Sun; Xiaole Cui; Yongliang Chen; Xiaoxin Cui (AsianHOST, 2021)

Design and Implementation of Full Adder in One-Transistor-One-Resistor RRAM Array. - Xiangyu Zhang; Feng Wei; Xiaoyan Liu; Xiaole Cui (ASICON, 2021)

The Modeling Attack and Security Enhancement of the XbarPUF with Both Column Swapping and XORing. - Yongliang Chen; Xiaole Cui; Wenqiang Ye; Xiaoxin Cui (ACM Great Lakes Symposium on VLSI, 2021)

An SNN-Based and Neuromorphic-Hardware-Implementable Noise Filter with Self-adaptive Time Window for Event-Based Vision Sensor. - Kanglin Xiao; Xiaoxin Cui; Kefei Liu 002; Xiaole Cui; Xin'an Wang (IJCNN, 2021)

The ANN Based Modeling Attack and Security Enhancement of the Double-layer PUF. - Xiaole Cui; Yongliang Chen; Wenqiang Ye; Xiaoxin Cui (ITC-Asia, 2021)

The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack. - Yongliang Chen; Xiaole Cui; Wenqiang Ye; Xiaoxin Cui (ITC, 2021)

The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates. - Xiaole Cui; Ye Ma; Feng Wei; Xiaoxin Cui (IEEE Access, 2021)

28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance. - Qingyun Zou; Xiaoxin Cui; Zhenhui Dai; Yisong Kuang; Yi Zhong; Chenglong Zou; Xiaole Cui (IEICE Electron. Express, 2021)

Machine Learning Aided Key-Guessing Attack Paradigm Against Logic Block Encryption. - Yi Zhong; Jianhua Feng; Xiaoxin Cui; Xiaole Cui (J. Comput. Sci. Technol., 2021)

An obfuscation scheme of scan chain to protect the cryptographic chips. - Huixian Huang; Xiaole Cui; Shuming Zhang; Ge Li; Xiaoxin Cui (ATS, 2022)

The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates. - Fan Liu; Sunrui Zhang; Xiaole Cui (FPL, 2022)

A Modeling Attack on the Sub-threshold Current Array PUF. - Yun Liu; Yongliang Chen; Xiaole Cui (HOST, 2022)

An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells. - Xiaole Cui; Fan Liu; Sunrui Zhang; Xiaoxin Cui (ISCAS, 2022)

A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec. - Chen Wei; Xiaole Cui; Xiaoxin Cui (IEEE Des. Test, 2022)

An Anti-Removal-Attack Hardware Watermarking Method Based on Polymorphic Gates. - Yongliang Chen; Xiaole Cui; Pengyuan Yang; Gang Qu 001 (ICCAD, 2023)

An Evaluation Method of the Anti-Modeling-Attack Capability of PUFs. - Yongliang Chen; Xiaole Cui; Yun Liu; Xiaoxin Cui (IEEE Trans. Inf. Forensics Secur., 2023)

Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array. - Xiaole Cui; Chen Wei; Xu Feng; Xiaoxin Cui (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array. - Sunrui Zhang; Xiaole Cui; Feng Wei; Xiaoxin Cui (IEEE Trans. Computers, 2023)

A Convolutional Spiking Neural Network Accelerator with the Sparsity-Aware Memory and Compressed Weights. - Hanqing Liu; Xiaole Cui; Sunrui Zhang; Mingqi Yin; Yuanyuan Jiang; Xiaoxin Cui (ASAP, 2024)

A Testability Improvement Method of Combinational Circuits Based on the SDC Conditions. - Yang Zeng; Xiaole Cui (ATS, 2024)

Modeling Attack Tests and Security Enhancement of the Sub-Threshold Voltage Divider Array PUF. - Shengjie Zhou; Yongliang Chen; Xiaole Cui; Yun Liu (DATE, 2024)

SPAT: FPGA-based Sparsity-Optimized Spiking Neural Network Training Accelerator with Temporal Parallel Dataflow. - Yuanyuan Jiang; Li Lun; Jiawei Wang; Mingqi Yin; Hanqing Liu; Zhenhui Dai; Xiaole Cui; Xiaoxin Cui (ISCAS, 2024)

A High Performance PODEM Algorithm with the Improved Backtrace Process. - Yang Zeng; Xiaole Cui (ITC-Asia, 2024)

A reconfigurable FPGA-based spiking neural network accelerator. - Mingqi Yin; Xiaole Cui; Feng Wei; Hanqing Liu; Yuanyuan Jiang; Xiaoxin Cui (Microelectron. J., 2024)

The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells. - Xiaole Cui; Mingqi Yin; Hanqing Liu; Xiaoxin Cui (ACM Trans. Design Autom. Electr. Syst., 2024)

The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice. - Yongliang Chen; Xiaole Cui; Xiaoxin Cui; Xing Zhang 002 (Microelectron. J., 2024)

Dy-MFNS-CAC: An Encoding Mechanism to Suppress the Crosstalk and Repair the Hard Faults in Rectangular TSV Arrays. - Chen Wei; Xiaole Cui; Xiaoxin Cui (IEEE Trans. Reliab., 2024)

An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations. - Feng Wei; Xiaole Cui; Sunrui Zhang; Xing Zhang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An in-Array Build-In Self-Test Scheme for Embedded SRAM Array. - Feng Wei; Xiaole Cui; Sunrui Zhang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A UCIe Compatible Repair Scheme for the Clustered Faults in the Hexagonal Array of Interconnect Lanes. - Zhaohong Lin; Xiaole Cui; Juncheng Pu; Huan Yang (ETS, 2025)

In-Memory Logic Synthesis Methods based on Read Decoupled 8T and Transpose 11T SRAMs. - Feng Wei; Xiaole Cui; Sunrui Zhang (ISCAS, 2025)

A Network-Coding-Based Functional Test Method for Routers in 3-D Mesh NoCs. - Chen Wei; Xiaole Cui (IEEE Internet Things J., 2025)