Power and Timing Side Channels for PUFs and their Efficient Exploitation. - Ulrich Rührmair; Xiaolin Xu 001; Jan Sölter; Ahmed Mahmoud; Farinaz Koushanfar; Wayne P. Burleson (IACR Cryptol. ePrint Arch., 2013)

PUF Modeling Attacks on Simulated and Silicon Data. - Ulrich Rührmair; Jan Sölter; Frank Sehnke; Xiaolin Xu 001; Ahmed Mahmoud; Vera Stoyanova; Gideon Dror; Jürgen Schmidhuber; Wayne P. Burleson; Srinivas Devadas (IEEE Trans. Inf. Forensics Secur., 2013)

Efficient Power and Timing Side Channels for Physical Unclonable Functions. - Ulrich Rührmair; Xiaolin Xu 001; Jan Sölter; Ahmed Mahmoud; Mehrdad Majzoobi; Farinaz Koushanfar; Wayne P. Burleson (CHES, 2014)

Hybrid side-channel/machine-learning attacks on PUFs: A new threat? - Xiaolin Xu 001; Wayne P. Burleson (DATE, 2014)

Post-Silicon Validation and Calibration of Hardware Security Primitives. - Xiaolin Xu 001; Vikram B. Suresh; Raghavan Kumar; Wayne P. Burleson (ISVLSI, 2014)

Virtual Proofs of Reality and their Physical Implementation. - Ulrich Rührmair; J. L. Martinez-Hurtado; Xiaolin Xu 001; Christian Kraeh; Christian Hilgers; Dima Kononchuk; Jonathan J. Finley; Wayne P. Burleson (IEEE Symposium on Security and Privacy, 2015)

PLayPUF: Programmable Logically Erasable PUFs for Forward and Backward Secure Key Management. - Chenglu Jin; Xiaolin Xu 001; Wayne P. Burleson; Ulrich Rührmair; Marten van Dijk (IACR Cryptol. ePrint Arch., 2015)

Security Evaluation and Enhancement of Bistable Ring PUFs. - Xiaolin Xu 001; Ulrich Rührmair; Daniel E. Holcomb; Wayne P. Burleson (IACR Cryptol. ePrint Arch., 2015)

Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells. - Xiaolin Xu 001; Amir Rahmati; Daniel E. Holcomb; Kevin Fu; Wayne P. Burleson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Reliable PUF design using failure patterns from time-controlled power gating. - Xiaolin Xu 001; Daniel E. Holcomb (DFT, 2016)

A Clockless Sequential PUF with Autonomous Majority Voting. - Xiaolin Xu 001; Daniel E. Holcomb (ACM Great Lakes Symposium on VLSI, 2016)

Using Statistical Models to Improve the Reliability of Delay-Based PUFs. - Xiaolin Xu 001; Wayne P. Burleson; Daniel E. Holcomb (ISVLSI, 2016)

MPA: Model-assisted PCB attestation via board-level RO and temperature compensation. - Zimu Guo; Xiaolin Xu 001; Mark Tehranipoor; Domenic Forte (AsianHOST, 2017)

FFD: A Framework for Fake Flash Detection. - Zimu Guo; Xiaolin Xu 001; Mark Tehranipoor; Domenic Forte (DAC, 2017)

CCATDC: A Configurable Compact Algorithmic Time-to-Digital Converter. - Shuo Li; Xiaolin Xu 001; Wayne P. Burleson (ISVLSI, 2017)

Aging resilient RO PUF with increased reliability in FPGA. - Sreeja Chowdhury; Xiaolin Xu 001; Mark Tehranipoor; Domenic Forte (ReConFig, 2017)

Novel Bypass Attack and BDD-based Tradeoff Analysis Against all Known Logic Locking Attacks. - Xiaolin Xu 001; Bicky Shakya; Mark Tehranipoor; Domenic Forte (IACR Cryptol. ePrint Arch., 2017)

Security Beyond CMOS: Fundamentals, Applications, and Roadmap. - Fahim Rahman; Bicky Shakya; Xiaolin Xu 001; Domenic Forte; Mark Tehranipoor (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Poly-Si-Based Physical Unclonable Functions. - Hao-Ting Shen; Fahim Rahman; Bicky Shakya; Xiaolin Xu 001; Mark Tehranipoor; Domenic Forte (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Power-based side-channel instruction-level disassembler. - Jungmin Park; Xiaolin Xu 001; Yier Jin; Domenic Forte; Mark Tehranipoor (DAC, 2018)

Efficient Erasable PUFs from Programmable Logic and Memristors. - Yansong Gao 001; Chenglu Jin; Jeeson Kim; Hussein Nili; Xiaolin Xu 001; Wayne P. Burleson; Omid Kavehei; Marten van Dijk; Damith Chinthana Ranasinghe; Ulrich Rührmair (IACR Cryptol. ePrint Arch., 2018)

Development and Evaluation of Hardware Obfuscation Benchmarks. - Sarah Amir; Bicky Shakya; Xiaolin Xu 001; Yier Jin; Swarup Bhunia; Mark Tehranipoor; Domenic Forte (J. Hardw. Syst. Secur., 2018)

Survey on Applications of Formal Methods in Reverse Engineering and Intellectual Property Protection. - Shahrzad Keshavarz; Cunxi Yu; Samaneh Ghandali; Xiaolin Xu 001; Daniel E. Holcomb (J. Hardw. Syst. Secur., 2018)

SCARe: An SRAM-Based Countermeasure Against IC Recycling. - Zimu Guo; Xiaolin Xu 001; Md. Tauhidur Rahman 001; Mark Tehranipoor; Domenic Forte (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs. - Xiaolin Xu 001; Shahrzad Keshavarz; Domenic Forte; Mark Tehranipoor; Daniel E. Holcomb (IEEE Trans. Very Large Scale Integr. Syst., 2018)

An All-Digital True Random Number Generator Based on Chaotic Cellular Automata Topology. - Scott Best; Xiaolin Xu 001 (ICCAD, 2019)

HILL: A Hardware Isolation Framework Against Information Leakage on Multi-Tenant FPGA Long-Wires. - Yukui Luo; Xiaolin Xu 001 (FPT, 2019)

PVTMC: An All-Digital Sub-Picosecond Timing Measurement Circuit Based on Process Variations. - Shuo Li; Xiaolin Xu 001; Wayne P. Burleson (ISVLSI, 2019)

EOP: An Encryption-Obfuscation Solution for Protecting PCBs Against Tampering and Reverse Engineering. - Zimu Guo; Xiaolin Xu 001; Mark Tehranipoor; Domenic Forte (CoRR, 2019)

Electronics Supply Chain Integrity Enabled by Blockchain. - Xiaolin Xu 001; Fahim Rahman; Bicky Shakya; Apostol Vassilev 001; Domenic Forte; Mark Tehranipoor (ACM Trans. Design Autom. Electr. Syst., 2019)

A Dynamic Frequency Scaling Framework Against Reliability and Security Issues in Multi-tenant FPGA. - Yukui Luo; Xiaolin Xu 001 (FCCM, 2020)

A Privacy-Preserving-Oriented DNN Pruning and Mobile Acceleration Framework. - Yifan Gong 004; Zheng Zhan 001; Zhengang Li; Wei Niu 002; Xiaolong Ma; Wenhao Wang 001; Bin Ren; Caiwen Ding; Xue Lin 001; Xiaolin Xu 001; Yanzhi Wang (ACM Great Lakes Symposium on VLSI, 2020)

A Quantitative Defense Framework against Power Attacks on Multi-tenant FPGA. - Yukui Luo; Xiaolin Xu 001 (ICCAD, 2020)

Stealthy-Shutdown: Practical Remote Power Attacks in Multi - Tenant FPGAs. - Yukui Luo; Cheng Gongye; Shaolei Ren; Yunsi Fei; Xiaolin Xu 001 (ICCD, 2020)

Rethinking FPGA Security in the New Era of Artificial Intelligence. - Xiaolin Xu 001; Jiliang Zhang 002 (ISQED, 2020)

A Privacy-Preserving DNN Pruning and Mobile Acceleration Framework. - Zheng Zhan 001; Yifan Gong 004; Zhengang Li; Pu Zhao 001; Xiaolong Ma; Wei Niu 002; Xiaolin Xu 001; Bin Ren; Yanzhi Wang; Xue Lin 001 (CoRR, 2020)

Defeating CAS-Unlock. - Bicky Shakya; Xiaolin Xu 001; Mark Tehranipoor; Domenic Forte (IACR Cryptol. ePrint Arch., 2020)

A High-Performance and Secure TRNG Based on Chaotic Cellular Automata Topology. - Yukui Luo; Wenhao Wang 001; Scott Best; Yanzhi Wang; Xiaolin Xu 001 (IEEE Trans. Circuits Syst., 2020)

CAS-Lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme. - Bicky Shakya; Xiaolin Xu 001; Mark Tehranipoor; Domenic Forte (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020)

DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA. - Yukui Luo; Cheng Gongye; Yunsi Fei; Xiaolin Xu 001 (DAC, 2021)

SGX-FPGA: Trusted Execution Environment for CPU-FPGA Heterogeneous Architecture. - Ke Xia; Yukui Luo; Xiaolin Xu 001; Sheng Wei 001 (DAC, 2021)

Constructive Use of Process Variations: Reconfigurable and High-Resolution Delay-Line. - Wenhao Wang 001; Yukui Luo; Xiaolin Xu 001 (DATE, 2021)

A Survey of Recent Attacks and Mitigation on FPGA Systems. - Shijin Duan; Wenhao Wang 001; Yukui Luo; Xiaolin Xu 001 (ISVLSI, 2021)

HDCOG: A Lightweight Hyperdimensional Computing Framework with Feature Extraction. - Shijin Duan; Xiaolin Xu 001 (NANOARCH, 2021)

Deep Neural Network Security From a Hardware Perspective. - Tong Zhou 002; Yuheng Zhang; Shijin Duan; Yukui Luo; Xiaolin Xu 001 (NANOARCH, 2021)

Deep-Dup: An Adversarial Weight Duplication Attack Framework to Crush Deep Neural Network in Multi-Tenant FPGA. - Adnan Siraj Rakin; Yukui Luo; Xiaolin Xu 001; Deliang Fan (USENIX Security Symposium, 2021)

LeHDC: learning-based hyperdimensional computing classifier. - Shijin Duan; Yejia Liu; Shaolei Ren; Xiaolin Xu 001 (DAC, 2022)

HDLock: exploiting privileged encoding to protect hyperdimensional computing models against IP stealing. - Shijin Duan; Shaolei Ren; Xiaolin Xu 001 (DAC, 2022)

NNReArch: A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse Engineering. - Yukui Luo; Shijin Duan; Cheng Gongye; Yunsi Fei; Xiaolin Xu 001 (FCCM, 2022)

An Integrity Checking Framework for AXI Protocol in Multi-tenant FPGA. - Yukui Luo; Yuheng Zhang; Shijin Duan; Xiaolin Xu 001 (FPGA, 2022)

A Cautionary Note on Building Multi-tenant Cloud-FPGA as a Secure Infrastructure. - Yukui Luo; Yuheng Zhang; Shijin Duan; Xiaolin Xu 001 (FPT, 2022)

ObfuNAS: A Neural Architecture Search-Based DNN Obfuscation Approach. - Tong Zhou 002; Shaolei Ren; Xiaolin Xu 001 (ICCAD, 2022)

A Brain-Inspired Low-Dimensional Computing Classifier for Inference on Tiny Devices. - Shijin Duan; Xiaolin Xu 001; Shaolei Ren (CoRR, 2022)

STT-MRAM-Based Reliable Weak PUF. - Yupeng Hu; Linjun Wu; Zhuojun Chen; Yun Huang; Xiaolin Xu 001; Keqin Li 001; Jiliang Zhang 002 (IEEE Trans. Computers, 2022)

FLAM-PUF: A Response-Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF. - Linjun Wu; Yupeng Hu; Kehuan Zhang; Wenjia Li; Xiaolin Xu 001; Wanli Chang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

CRAlert: Hardware-Assisted Code Reuse Attack Detection. - Wenhao Wang 001; Guangyu Hu; Xiaolin Xu 001; Jiliang Zhang 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA. - Yukui Luo; Shijin Duan; Xiaolin Xu 001 (ACM Trans. Design Autom. Electr. Syst., 2022)

HammerDodger: A Lightweight Defense Framework against RowHammer Attack on DNNs. - Cheng Gongye; Yukui Luo; Xiaolin Xu 001; Yunsi Fei (DAC, 2023)

PASNet: Polynomial Architecture Search Framework for Two-party Computation-based Secure Neural Network Deployment. - Hongwu Peng; Shanglin Zhou; Yukui Luo; Nuo Xu; Shijin Duan; Ran Ran; Jiahui Zhao; Chenghong Wang; Tong Geng; Wujie Wen; Xiaolin Xu 001; Caiwen Ding (DAC, 2023)

MirrorNet: A TEE-Friendly Framework for Secure On-Device DNN Inference. - Ziyu Liu; Yukui Luo; Shijin Duan; Tong Zhou 002; Xiaolin Xu 001 (ICCAD, 2023)

VertexSerum: Poisoning Graph Neural Networks for Link Inference. - Ruyi Ding; Shijin Duan; Xiaolin Xu 001; Yunsi Fei (ICCV, 2023)

AutoReP: Automatic ReLU Replacement for Fast Private Network Inference. - Hongwu Peng; Shaoyi Huang; Tong Zhou 002; Yukui Luo; Chenghong Wang; Zigeng Wang; Jiahui Zhao; Xi Xie; Ang Li 006; Tony Geng; Kaleel Mahmood; Wujie Wen; et al. (ICCV, 2023)

SpENCNN: Orchestrating Encoding and Sparsity for Fast Homomorphically Encrypted Neural Network Inference. - Ran Ran; Xinwei Luo; Wei Wang; Tao Liu 023; Gang Quan; Xiaolin Xu 001; Caiwen Ding; Wujie Wen (ICML, 2023)

NNSplitter: An Active Defense Solution for DNN Model via Automated Weight Obfuscation. - Tong Zhou 002; Yukui Luo; Shaolei Ren; Xiaolin Xu 001 (ICML, 2023)

Achieving Certified Robustness for Brain-Inspired Low-Dimensional Computing Classifiers. - Fangfang Yang; Shijin Duan; Xiaolin Xu 001; Shaolei Ren (INFOCOM Workshops, 2023)

AQ2PNN: Enabling Two-party Privacy-Preserving Deep Neural Network Inference with Adaptive Quantization. - Yukui Luo; Nuo Xu; Hongwu Peng; Chenghong Wang; Shijin Duan; Kaleel Mahmood; Wujie Wen; Caiwen Ding; Xiaolin Xu 001 (MICRO, 2023)

LinGCN: Structural Linearized Graph Convolutional Network for Homomorphically Encrypted Inference. - Hongwu Peng; Ran Ran; Yukui Luo; Jiahui Zhao; Shaoyi Huang; Kiran Thorat; Tong Geng; Chenghong Wang; Xiaolin Xu 001; Wujie Wen; Caiwen Ding (NeurIPS, 2023)

RRNet: Towards ReLU-Reduced Neural Network for Two-party Computation Based Private Inference. - Hongwu Peng; Shanglin Zhou; Yukui Luo; Nuo Xu; Shijin Duan; Ran Ran; Jiahui Zhao; Shaoyi Huang; Xi Xie; Chenghong Wang; Tong Geng; Wujie Wen; et al. (CoRR, 2023)

MetaLDC: Meta Learning of Low-Dimensional Computing Classifiers for Fast On-Device Adaption. - Yejia Liu; Shijin Duan; Xiaolin Xu 001; Shaolei Ren (CoRR, 2023)

NNSplitter: An Active Defense Solution to DNN Model via Automated Weight Obfuscation. - Tong Zhou 002; Yukui Luo; Shaolei Ren; Xiaolin Xu 001 (CoRR, 2023)

MicroVSA: An Ultra-Lightweight Vector Symbolic Architecture-based Classifier Library for Always-On Inference on Tiny Microcontrollers. - Nuntipat Narkthong; Shijin Duan; Shaolei Ren; Xiaolin Xu 001 (ASPLOS (2), 2024)

TBNet: A Neural Architectural Defense Framework Facilitating DNN Model Protection in Trusted Execution Environments. - Ziyu Liu; Tong Zhou 002; Yukui Luo; Xiaolin Xu 001 (DAC, 2024)

AdaPI: Facilitating DNN Model Adaptivity for Efficient Private Inference in Edge Computing. - Tong Zhou 002; Jiahui Zhao; Yukui Luo; Xi Xie; Wujie Wen; Caiwen Ding; Xiaolin Xu 001 (ICCAD, 2024)

ArchLock: Locking DNN Transferability at the Architecture Level with a Zero-Cost Binary Predictor. - Tong Zhou 002; Shaolei Ren; Xiaolin Xu 001 (ICLR, 2024)

Bileve: Securing Text Provenance in Large Language Models Against Spoofing with Bi-level Signature. - Tong Zhou 002; Xuandong Zhao; Xiaolin Xu 001; Shaolei Ren (NeurIPS, 2024)

GraphCroc: Cross-Correlation Autoencoder for Graph Structural Reconstruction. - Shijin Duan; Ruyi Ding; Jiaxing He; Aidong Adam Ding; Yunsi Fei; Xiaolin Xu 001 (NeurIPS, 2024)

Side-Channel-Assisted Reverse-Engineering of Encrypted DNN Hardware Accelerator IP and Attack Surface Exploration. - Cheng Gongye; Yukui Luo; Xiaolin Xu 001; Yunsi Fei (SP, 2024)

DeepShuffle: A Lightweight Defense Framework against Adversarial Fault Injection Attacks on Deep Neural Networks in Multi-Tenant Cloud-FPGA. - Yukui Luo; Adnan Siraj Rakin; Deliang Fan; Xiaolin Xu 001 (SP, 2024)

ALLI/O Diagram: An Action-based Visual Programming Language for Embedded System. - Nuntipat Narkthong; Chattriya Jariyavajee; Xiaolin Xu 001 (VL/HCC, 2024)

Scheduled Knowledge Acquisition on Lightweight Vector Symbolic Architectures for Brain-Computer Interfaces. - Yejia Liu; Shijin Duan; Xiaolin Xu 001; Shaolei Ren (CoRR, 2024)

SSNet: A Lightweight Multi-Party Computation Scheme for Practical Privacy-Preserving Machine Learning Service in the Cloud. - Shijin Duan; Chenghong Wang; Hongwu Peng; Yukui Luo; Wujie Wen; Caiwen Ding; Xiaolin Xu 001 (CoRR, 2024)

Brain Tumor Classification on MRI in Light of Molecular Markers. - Jun Liu 075; Geng Yuan; Weihao Zeng; Hao Tang 005; Wenbin Zhang 002; Xue Lin 001; Xiaolin Xu 001; Dong Huang; Yanzhi Wang (CoRR, 2024)

Towards Vector Optimization on Low-Dimensional Vector Symbolic Architecture. - Shijin Duan; Yejia Liu; Gaowen Liu; Ramana Rao Kompella; Shaolei Ren; Xiaolin Xu 001 (CPAL, 2025)

Probe-Me-Not: Protecting Pre-trained Encoders from Malicious Probing. - Ruyi Ding; Tong Zhou 002; Lili Su; Aidong Adam Ding; Xiaolin Xu 001; Yunsi Fei (NDSS, 2025)

ProDiF: Protecting Domain-Invariant Features to Secure Pre-Trained Models Against Extraction. - Tong Zhou 002; Shijin Duan; Gaowen Liu; Charles Fleming; Ramana Rao Kompella; Shaolei Ren; Xiaolin Xu 001 (CoRR, 2025)