Pre-silicon security verification and validation: a formal perspective. - Xiaolong Guo 001; Raj Gautam Dutta; Yier Jin; Farimah Farahmandi; Prabhat Mishra 001 (DAC, 2015)

Hierarchy-Preserving Formal Verification Methods for Pre-silicon Security Assurance. - Xiaolong Guo 001; Raj Gautam Dutta; Yier Jin (MTV, 2015)

Scalable SoC trust verification using integrated theorem proving and model checking. - Xiaolong Guo 001; Raj Gautam Dutta; Prabhat Mishra 001; Yier Jin (HOST, 2016)

Automatic RTL-to-Formal Code Converter for IP Security Formal Verification. - Xiaolong Guo 001; Raj Gautam Dutta; Prabhat Mishra 001; Yier Jin (MTV, 2016)

Quantifying trust in autonomous system under uncertainties. - Raj Gautam Dutta; Xiaolong Guo 001; Yier Jin (SoCC, 2016)

PCH framework for IP runtime security verification. - Xiaolong Guo 001; Raj Gautam Dutta; Jiaji He; Yier Jin (AsianHOST, 2017)

Estimation of Safe Sensor Measurements of Autonomous System Under Attack. - Raj Gautam Dutta; Xiaolong Guo 001; Teng Zhang 002; Kevin A. Kwiat; Charles A. Kamhoua; Laurent Njilla; Yier Jin (DAC, 2017)

Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part II: Framework Automation. - Mohammad-Mahdi Bidmeshki; Xiaolong Guo 001; Raj Gautam Dutta; Yier Jin; Yiorgos Makris (IEEE Trans. Inf. Forensics Secur., 2017)

Eliminating the Hardware-Software Boundary: A Proof-Carrying Approach for Trust Evaluation on Computer Systems. - Xiaolong Guo 001; Raj Gautam Dutta; Yier Jin (IEEE Trans. Inf. Forensics Secur., 2017)

Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part I: Framework Fundamentals. - Yier Jin; Xiaolong Guo 001; Raj Gautam Dutta; Mohammad-Mahdi Bidmeshki; Yiorgos Makris (IEEE Trans. Inf. Forensics Secur., 2017)

Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification. - Xiaolong Guo 001; Raj Gautam Dutta; Prabhat Mishra 001; Yier Jin (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Hardware Trojan Detection Through Chip-Free Electromagnetic Side-Channel Statistical Analysis. - Jiaji He; Yiqiang Zhao; Xiaolong Guo 001; Yier Jin (IEEE Trans. Very Large Scale Integr. Syst., 2017)

When Capacitors Attack: Formal Method Driven Design and Detection of Charge-Domain Trojans. - Xiaolong Guo 001; Huifeng Zhu; Yier Jin; Xuan Zhang 001 (DATE, 2019)

QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment. - Xiaolong Guo 001; Raj Gautam Dutta; Jiaji He; Mark Tehranipoor; Yier Jin (HOST, 2019)

Hardware and Software Co-Verification from Security Perspective. - Kejun Chen; Qingxu Deng; Yumin Hou; Yier Jin; Xiaolong Guo 001 (MTV, 2019)

SoC interconnection protection through formal verification. - Jiaji He; Xiaolong Guo 001; Travis Meade; Raj Gautam Dutta; Yiqiang Zhao; Yier Jin (Integr., 2019)

PowerScout: A Security-Oriented Power Delivery Network Modeling Framework for Cross-Domain Side-Channel Analysis. - Huifeng Zhu; Xiaolong Guo 001; Yier Jin; Xuan Zhang 001 (AsianHOST, 2020)

Design for EM Side-Channel Security through Quantitative Assessment of RTL Implementations. - Jiaji He; Haocheng Ma; Xiaolong Guo 001; Yiqiang Zhao; Yier Jin (ASP-DAC, 2020)

Runtime Trust Evaluation and Hardware Trojan Detection Using On-Chip EM Sensors. - Jiaji He; Xiaolong Guo 001; Haocheng Ma; Yanjiang Liu; Yiqiang Zhao; Yier Jin (DAC, 2020)

PCBench: Benchmarking of Board-Level Hardware Attacks and Trojans. - Huifeng Zhu; Xiaolong Guo 001; Yier Jin; Xuan Zhang 001 (ASP-DAC, 2021)

Quantifying Rowhammer Vulnerability for DRAM Security. - Yichen Jiang; Huifeng Zhu; Dean Sullivan; Xiaolong Guo 001; Xuan Zhang 001; Yier Jin (DAC, 2021)

Towards scalable, secure, and smart mission-critical IoT systems: review and vision. - Xiaolong Guo 001; Song Han 002; X. Sharon Hu; Xun Jiao 002; Yier Jin; Fanxin Kong; Michael Lemmon 001 (EMSOFT, 2021)

TRRScope: Understanding Target Row Refresh Mechanism for Modern DDR Protection. - Yichen Jiang; Huifeng Zhu; Haoqi Shan; Xiaolong Guo 001; Xuan Zhang 001; Yier Jin (HOST, 2021)

Fuzzing Hardware: Faith or Reality? : Invited Paper. - Weimin Fu; Orlando Arias; Yier Jin; Xiaolong Guo 001 (NANOARCH, 2021)

RTSEC: Automated RTL Code Augmentation for Hardware Security Enhancement. - Orlando Arias; Zhaoxiang Liu; Xiaolong Guo 001; Yier Jin; Shuo Wang 003 (DATE, 2022)

Inter-IP Malicious Modification Detection through Static Information Flow Tracking. - Zhaoxiang Liu; Orlando Arias; Weimin Fu; Yier Jin; Xiaolong Guo 001 (DATE, 2022)

Graph Neural Network based Hardware Trojan Detection at Intermediate Representative for SoC Platforms. - Weimin Fu; Honggang Yu; Orlando Arias; Kaichen Yang; Yier Jin; Tuba Yavuz; Xiaolong Guo 001 (ACM Great Lakes Symposium on VLSI, 2022)

EM Side Channels in Hardware Security: Attacks and Defenses. - Jiaji He; Xiaolong Guo 001; Mark Tehranipoor; Apostol Vassilev 001; Yier Jin (IEEE Des. Test, 2022)

Security Oriented Design Framework for EM Side-Channel Protection in RTL Implementations. - Jiaji He; Haocheng Ma; Max Panoff; Hanning Wang; Yiqiang Zhao; Leibo Liu; Xiaolong Guo 001; Yier Jin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

FineDIFT: Fine-Grained Dynamic Information Flow Tracking for Data-Flow Integrity Using Coprocessor. - Kejun Chen; Orlando Arias; Qingxu Deng; Daniela Oliveira 001; Xiaolong Guo 001; Yier Jin (IEEE Trans. Inf. Forensics Secur., 2022)

VGF: Value-Guided Fuzzing - Fuzzing Hardware as Hardware. - Ruochen Dai; Michael Lee; Patrick Hoey; Weimin Fu; Tuba Yavuz; Xiaolong Guo 001; Shuo Wang 003; Dean Sullivan; Orlando Arias (CoRR, 2023)

IP-Tag: Tag-Based Runtime 3PIP Hardware Trojan Detection in SoC Platforms. - Kejun Chen; Orlando Arias; Xiaolong Guo 001; Qingxu Deng; Yier Jin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

PDNPulse: Sensing PCB Anomaly With the Intrinsic Power Delivery Network. - Huifeng Zhu; Haoqi Shan; Dean Sullivan; Xiaolong Guo 001; Yier Jin; Xuan Zhang 001 (IEEE Trans. Inf. Forensics Secur., 2023)

Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge. - Weimin Fu; Shijie Li 009; Yifang Zhao; Haocheng Ma; Raj Gautam Dutta; Xuan Zhang 001; Kaichen Yang; Yier Jin; Xiaolong Guo 001 (ASPDAC, 2024)

Microscope: Causality Inference Crossing the Hardware and Software Boundary from Hardware Perspective. - Zhaoxiang Liu; Kejun Chen; Dean Sullivan; Orlando Arias; Raj Gautam Dutta; Yier Jin; Xiaolong Guo 001 (ASPDAC, 2024)

Poster: Enhance Hardware Domain Specific Large Language Model with Reinforcement Learning for Resilience. - Weimin Fu; Yifang Zhao; Yier Jin; Xiaolong Guo 001 (CCS, 2024)

Poster: BlindMarket: A Trustworthy Chip Designs Marketplace for IP Vendors and Users. - Zhaoxiang Liu; Ning Luo; Samuel Judson; Raj Gautam Dutta; Xiaolong Guo 001; Mark Santolucito (CCS, 2024)

DTjRTL: A Configurable Framework for Automated Hardware Trojan Insertion at RTL. - Ruochen Dai; Zhaoxiang Liu; Orlando Arias; Xiaolong Guo 001; Tuba Yavuz (ACM Great Lakes Symposium on VLSI, 2024)

PowerScout: Security-Oriented Power Delivery Network Modeling for Side-Channel Vulnerability Analysis. - Huifeng Zhu; Xiaolong Guo 001; Yier Jin; Xuan Zhang 001 (IEEE Trans. Emerg. Top. Comput., 2024)

EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog Circuits. - Jian Gao; Weimin Fu; Xiaolong Guo 001; Weidong Cao 001; Xuan Zhang 001 (DAC, 2025)

Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs. - Yifang Zhao; Weimin Fu; Shijie Li 009; Yi-Xiang Hu; Xiaolong Guo 001; Yier Jin (DAC, 2025)

HWFixBench: Benchmarking Tools for Hardware Understanding and Fault Repair. - Weimin Fu; Shijie Li 009; Yier Jin; Xiaolong Guo 001 (ACM Great Lakes Symposium on VLSI, 2025)

Intelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLM. - Shijie Li 009; Weimin Fu; Yifang Zhao; Xiaolong Guo 001; Yier Jin (ACM Great Lakes Symposium on VLSI, 2025)

Evaluating the Effectiveness of Hardware Trojan Detection Approaches at RTL. - Ruochen Dai; Zhaoxiang Liu; Orlando Arias; Xiaolong Guo 001; Tuba Yavuz (HOST, 2025)

Enhancing LLM Performance on Hardware Design Generation Task via Reinforcement Learning. - Yifang Zhao; Weimin Fu; Shijie Li 009; Yixiang Hu; Xiaolong Guo 001; Yier Jin (ISCAS, 2025)

Cross-Layer EM Fault Injection Assessment Framework. - Hanqiu Wang; Ruochen Dai; Tuba Yavuz; Xiaolong Guo 001; Orlando Arias; Dean Sullivan; Michael Lee; Honggang Yu; Siqi Dai; Domenic Forte; Shuo Wang 003 (ISQED, 2025)

A Generalize Hardware Debugging Approach for Large Language Models Semi-Synthetic, Datasets. - Weimin Fu; Shijie Li 009; Yifang Zhao; Kaichen Yang; Xuan Zhang 001; Yier Jin; Xiaolong Guo 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)