Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis. - Jianchao Lu; Xiaomi Mao; Baris Taskin (ISPD, 2011)

Clock mesh synthesis with gated local trees and activity driven register clustering. - Jianchao Lu; Xiaomi Mao; Baris Taskin (ICCAD, 2012)

Integrated Clock Mesh Synthesis With Incremental Register Placement. - Jianchao Lu; Xiaomi Mao; Baris Taskin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)