Xiaoming Chen
Orcid: 0000-0002-7337-1844Affiliations:
- Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China
- University of Notre Dame, Department of Computer Science and Engineering, Notre Dame, IN, USA (2016 - 2017)
- Carnegie Mellon University, Department of Electrical and Computer Engineering, Pittsburgh, PA, USA (2014 - 2016)
- Tsinghua University, Department of Electronic Engineering, Beijing, China (PhD 2014)
According to our database1,
Xiaoming Chen
authored at least 109 papers
between 2009 and 2024.
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Bibliography
2024
Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators.
ACM Trans. Design Autom. Electr. Syst., January, 2024
2023
Frequency-Domain Inference Acceleration for Convolutional Neural Networks Using ReRAMs.
IEEE Trans. Parallel Distributed Syst., December, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
CoRR, 2023
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
LIM-GEN: A Data-Guided Framework for Automated Generation of Heterogeneous Logic-in-Memory Architecture.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-Sharing Approach.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Embed. Syst. Lett., 2022
VNet: a versatile network to train real-time semantic segmentation models on a single GPU.
Sci. China Inf. Sci., 2022
Numerically-Stable and Highly-Scalable Parallel LU Factorization for Circuit Simulation.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022
Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022
P3S: A High Accuracy Probabilistic Prediction Processing System for CNN Acceleration.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
GraphRing: an HMC-ring based graph processing framework with optimized data movement.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Solving Least-Squares Fitting in $O(1)$ Using RRAM-based Computing-in-Memory Technique.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
ACM Trans. Design Autom. Electr. Syst., 2021
Chaotic Weights: A Novel Approach to Protect Intellectual Property of Deep Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology.
Sci. China Inf. Sci., 2021
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
CoPIM: A Concurrency-aware PIM Workload Offloading Architecture for Graph Applications.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
Eliminating Iterations of Iterative Methods: Solving Large-Scale Sparse Linear System in <i>O</i>(1) with RRAM-based In-Memory Accelerator.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
BRAHMS: Beyond Conventional RRAM-based Neural Network Accelerators Using Hybrid Analog Memory System.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption.
Proceedings of the 30th IEEE Asian Test Symposium, 2021
FePIM: Contention-Free In-Memory Computing Based on Ferroelectric Field-Effect Transistors.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Long Live TIME: Improving Lifetime and Security for NVM-Based Training-in-Memory Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Enabling Secure NVM-Based in-Memory Neural Network Computing by Sparse Fast Gradient Encryption.
IEEE Trans. Computers, 2020
IEEE Des. Test, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
TUPIM: A Transparent and Universal Processing-in-Memory Architecture for Unmodified Binaries.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Dadu-CD: Fast and Efficient Processing-in-Memory Accelerator for Collision Detection.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Parallel Distributed Syst., 2019
Dependable Visual Light-Based Indoor Localization with Automatic Anomaly Detection for Location-Based Service of Mobile Cyber-Physical Systems.
ACM Trans. Cyber Phys. Syst., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Thread: Towards fine-grained precision reconfiguration in variable-precision neural network accelerator.
IEICE Electron. Express, 2019
Sci. China Inf. Sci., 2019
IEEE Comput. Archit. Lett., 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
Enabling Secure in-Memory Neural Network Computing by Sparse Fast Gradient Encryption.
Proceedings of the International Conference on Computer-Aided Design, 2019
Merging Everything (ME): A Unified FPGA Architecture Based on Logic-in-Memory Techniques.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Design and optimization of FeFET-based crossbars for binary convolution neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Long live TIME: improving lifetime for training-in-memory engines by structured gradient sparsification.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
A General Framework for Hardware Trojan Detection in Digital Circuits by Statistical Learning Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
A Unified Methodology for Designing Hardware Random Number Generators Based on Any Probability Distribution.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Overview of cyber-physical temperature estimation in smart buildings: From modeling to measurements.
Proceedings of the IEEE Conference on Computer Communications Workshops, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
GPU-Accelerated Sparse LU Factorization for Circuit Simulation with Performance Modeling.
IEEE Trans. Parallel Distributed Syst., 2015
Proceedings of the 2015 IEEE International Test Conference, 2015
From Robust Chip to Smart Building: CAD Algorithms and Methodologies for Uncertainty Analysis of Building Performance.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits.
IET Circuits Devices Syst., 2013
Nonzero pattern analysis and memory access optimization in GPU-based sparse LU factorization for circuit simulation.
Proceedings of the 3rd Workshop on Irregular Applications - Architectures and Algorithms, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009