Gate replacement techniques for simultaneous leakage and aging optimization. - Yu Wang 002; Xiaoming Chen 003; Wenping Wang 004; Yu Cao 001; Yuan Xie 001; Huazhong Yang (DATE, 2009)

Variation-aware supply voltage assignment for minimizing circuit degradation and leakage. - Xiaoming Chen 003; Yu Wang 002; Yu Cao 001; Yuchun Ma; Huazhong Yang (ISLPED, 2009)

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power. - Yu Wang 002; Xiaoming Chen 003; Wenping Wang 004; Varsha Balakrishnan; Yu Cao 001; Yuan Xie 001; Huazhong Yang (ISQED, 2009)

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise. - Yan Xu; Weichen Liu; Yu Wang 002; Jiang Xu 001; Xiaoming Chen 003; Huazhong Yang (ISVLSI, 2009)

FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations. - Wei Wu; Yi Shan; Xiaoming Chen 003; Yu Wang 002; Huazhong Yang (ARC, 2011)

Circuit-level delay modeling considering both TDDB and NBTI. - Hong Luo; Xiaoming Chen 003; Jyothi Velamala; Yu Wang 002; Yu Cao 001; Vikas Chandra; Yuchun Ma; Huazhong Yang (ISQED, 2011)

An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation. - Xiaoming Chen 003; Wei Wu; Yu Wang 002; Hao Yu 001; Huazhong Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques. - Yu Wang 002; Xiaoming Chen 003; Wenping Wang 004; Yu Cao 001; Yuan Xie 001; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

An adaptive LU factorization algorithm for parallel circuit simulation. - Xiaoming Chen 003; Yu Wang 002; Huazhong Yang (ASP-DAC, 2012)

Sparse LU factorization for parallel circuit simulation on GPU. - Ling Ren 001; Xiaoming Chen 003; Yu Wang 002; Chenxi Zhang; Huazhong Yang (DAC, 2012)

Parallel Circuit Simulation on Multi/Many-core Systems. - Xiaoming Chen 003; Yu Wang 002; Huazhong Yang (IPDPS Workshops, 2012)

Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization. - Xiaoming Chen 003; Yu Wang 002; Yu Cao 001; Yuchun Ma; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

HS3DPG: Hierarchical simulation for 3D P/G network. - Shuai Tao; Xiaoming Chen 003; Yu Wang 002; Yuchun Ma; Yiyu Shi 001; Hui Wang 004; Huazhong Yang (ASP-DAC, 2013)

Nonzero pattern analysis and memory access optimization in GPU-based sparse LU factorization for circuit simulation. - Xiaoming Chen 003; Du Su; Yu Wang 002; Huazhong Yang (IA3@SC, 2013)

Assessment of Circuit Optimization Techniques Under NBTI. - Xiaoming Chen 003; Yu Wang 002; Huazhong Yang; Yuan Xie 001; Yu Cao 001 (IEEE Des. Test, 2013)

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits. - Xiaoming Chen 003; Hong Luo; Yu Wang 002; Yu Cao 001; Yuan Xie 001; Yuchun Ma; Huazhong Yang (IET Circuits Devices Syst., 2013)

NICSLU: An Adaptive Sparse Matrix Solver for Parallel Circuit Simulation. - Xiaoming Chen 003; Yu Wang 002; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Statistical analysis of random telegraph noise in digital circuits. - Xiaoming Chen 003; Yu Wang 002; Yu Cao 001; Huazhong Yang (ASP-DAC, 2014)

Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs. - Xiaoming Chen 003; Yu Wang 002; Yun Liang 001; Yuan Xie 001; Huazhong Yang (DAC, 2014)

Efficient region-aware P/G TSV planning for 3D ICs. - Song Yao; Xiaoming Chen 003; Yu Wang 002; Yuchun Ma; Yuan Xie 001; Huazhong Yang (ISQED, 2014)

A STT-RAM-based low-power hybrid register file for GPGPUs. - Gushu Li; Xiaoming Chen 003; Guangyu Sun 003; Henry Hoffmann; Yongpan Liu; Yu Wang 002; Huazhong Yang (DAC, 2015)

A fast parallel sparse solver for SPICE-based circuit simulators. - Xiaoming Chen 003; Yu Wang 002; Huazhong Yang (DATE, 2015)

From Robust Chip to Smart Building: CAD Algorithms and Methodologies for Uncertainty Analysis of Building Performance. - Xiaoming Chen 003; Xin Li 001; Sheldon X.-D. Tan (ICCAD, 2015)

FASTrust: Feature analysis for third-party IP trust verification. - Song Yao; Xiaoming Chen 003; Jie Zhang 046; Qiaoyi Liu; Jia Wang; Qiang Xu 001; Yu Wang 002; Huazhong Yang (ITC, 2015)

GPU-Accelerated Sparse LU Factorization for Circuit Simulation with Performance Modeling. - Xiaoming Chen 003; Ling Ren 001; Yu Wang 002; Huazhong Yang (IEEE Trans. Parallel Distributed Syst., 2015)

HS3-DPG: Hierarchical Simulation for 3-D P/G Network. - Yu Wang 002; Song Yao; Shuai Tao; Xiaoming Chen 003; Yuchun Ma; Yiyu Shi 001; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Sparsity-oriented sparse solver design for circuit simulation. - Xiaoming Chen 003; Lixue Xia; Yu Wang 002; Huazhong Yang (DATE, 2016)

Overview of cyber-physical temperature estimation in smart buildings: From modeling to measurements. - Xiaoming Chen 003; Xin Li 001; Sheldon X.-D. Tan (INFOCOM Workshops, 2016)

Virtual temperature measurement for smart buildings via Bayesian model fusion. - Xiaoming Chen 003; Xin Li 001 (ISCAS, 2016)

Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation. - Xiaoming Chen 003; Lin Wang; Boxun Li; Yu Wang 002; Xin Li 001; Yongpan Liu; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A Unified Methodology for Designing Hardware Random Number Generators Based on Any Probability Distribution. - Xiaoming Chen 003; Boxun Li; Yu Wang 002; Yongpan Liu; Huazhong Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Optimizing Memory Efficiency for Convolution Kernels on Kepler GPUs. - Xiaoming Chen 003; Jianxu Chen 001; Danny Z. Chen; Xiaobo Sharon Hu (DAC, 2017)

Low-overhead implementation of logic encryption using gate replacement techniques. - Xiaoming Chen 003; Qiaoyi Liu; Yu Wang 002; Qiang Xu 001; Huazhong Yang (ISQED, 2017)

A Deep Learning Approach for Blind Drift Calibration of Sensor Networks. - Yuzhi Wang; Anqi Yang; Xiaoming Chen 003; Pengjun Wang; Yu Wang 002; Huazhong Yang (CoRR, 2017)

A General Framework for Hardware Trojan Detection in Digital Circuits by Statistical Learning Algorithms. - Xiaoming Chen 003; Lin Wang; Yu Wang 002; Yongpan Liu; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Long live TIME: improving lifetime for training-in-memory engines by structured gradient sparsification. - Yi Cai 003; Yujun Lin 001; Lixue Xia; Xiaoming Chen 003; Song Han 003; Yu Wang 002; Huazhong Yang (DAC, 2018)

Dadu-P: a scalable accelerator for robot motion planning in a dynamic environment. - Shiqi Lian; Yinhe Han 001; Xiaoming Chen 003; Ying Wang 001; Hang Xiao (DAC, 2018)

Computing with ferroelectric FETs: Devices, models, systems, and applications. - Ahmedullah Aziz; Evelyn T. Breyer; An Chen; Xiaoming Chen 003; Suman Datta; Sumeet Kumar Gupta; Michael Hoffmann 008; Xiaobo Sharon Hu; Adrian M. Ionescu; Matthew Jerry; Thomas Mikolajick; Halid Mulaosmanovic; et al. (DATE, 2018)

moDNN: Memory optimal DNN training on GPUs. - Xiaoming Chen 003; Danny Z. Chen; Xiaobo Sharon Hu (DATE, 2018)

Design and optimization of FeFET-based crossbars for binary convolution neural networks. - Xiaoming Chen 003; Xunzhao Yin; Michael T. Niemier; Xiaobo Sharon Hu (DATE, 2018)

Rescuing memristor-based computing with non-linear resistance levels. - Jilan Lin; Lixue Xia; Zhenhua Zhu; Hanbo Sun; Yi Cai 003; Hui Gao; Ming Cheng; Xiaoming Chen 003; Yu Wang 002; Huazhong Yang (DATE, 2018)

Model-based and data-driven approaches for building automation and control. - Tianshu Wei; Xiaoming Chen 003; Xin Li 001; Qi Zhu 002 (ICCAD, 2018)

Mixed size crossbar based RRAM CNN accelerator with overlapped mapping method. - Zhenhua Zhu; Jilan Lin; Ming Cheng; Lixue Xia; Hanbo Sun; Xiaoming Chen 003; Yu Wang 002; Huazhong Yang (ICCAD, 2018)

Nonvolatile Lookup Table Design Based on Ferroelectric Field-Effect Transistors. - Xiaoming Chen 003; Michael T. Niemier; Xiaobo Sharon Hu (ISCAS, 2018)

Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis. - Xiaoming Chen 003; Qiaoyi Liu; Song Yao; Jia Wang; Qiang Xu 001; Yu Wang 002; Yongpan Liu; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators. - Bosheng Liu; Xiaoming Chen 003; Ying Wang 001; Yinhe Han 001; Jiajun Li; Haobo Xu; Xiaowei Li 001 (ASP-DAC, 2019)

CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems. - Sheng Xu; Xiaoming Chen 003; Ying Wang 001; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2019)

Merging Everything (ME): A Unified FPGA Architecture Based on Logic-in-Memory Techniques. - Xiaoming Chen 003; Longxiang Yin; Bosheng Liu; Yinhe Han 001 (DAC, 2019)

Enabling Secure in-Memory Neural Network Computing by Sparse Fast Gradient Encryption. - Yi Cai 003; Xiaoming Chen 003; Lu Tian; Yu Wang 002; Huazhong Yang (ICCAD, 2019)

A General Logic Synthesis Framework for Memristor-based Logic Design. - Zhenhua Zhu; Mingyuan Ma; Jialong Liu; Liying Xu; Xiaoming Chen 003; Yuchao Yang 001; Yu Wang 002; Huazhong Yang (ICCAD, 2019)

FeMAT: Exploring In-Memory Processing in Multifunctional FeFET-Based Memory Array. - Xiaoyu Zhang 009; Xiaoming Chen 003; Yinhe Han 001 (ICCD, 2019)

PIMSim: A Flexible and Detailed Processing-in-Memory Simulator. - Sheng Xu; Xiaoming Chen 003; Ying Wang 001; Yinhe Han 001; Xuehai Qian; Xiaowei Li 001 (IEEE Comput. Archit. Lett., 2019)

Accelerating DNN-based 3D point cloud processing for mobile computing. - Bosheng Liu; Xiaoming Chen 003; Yinhe Han 001; Jiajun Li; Haobo Xu; Xiaowei Li 001 (Sci. China Inf. Sci., 2019)

Thread: Towards fine-grained precision reconfiguration in variable-precision neural network accelerator. - Shichang Zhang; Ying Wang 001; Xiaoming Chen 003; Yinhe Han 001; Yujie Wang; Xiaowei Li 001 (IEICE Electron. Express, 2019)

Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs. - Xiaoming Chen 003; Kai Ni 004; Michael T. Niemier; Yinhe Han 001; Suman Datta; Xiaobo Sharon Hu (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Dependable Visual Light-Based Indoor Localization with Automatic Anomaly Detection for Location-Based Service of Mobile Cyber-Physical Systems. - Yang Liu 064; Xiaoming Chen 003; Dileep Kadambi; Ajinkya Bari; Xin Li 001; Shiyan Hu 001; Pingqiang Zhou (ACM Trans. Cyber Phys. Syst., 2019)

moDNN: Memory Optimal Deep Neural Network Training on Graphics Processing Units. - Xiaoming Chen 003; Danny Ziyi Chen; Yinhe Han 001; Xiaobo Sharon Hu (IEEE Trans. Parallel Distributed Syst., 2019)

Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits. - Xunzhao Yin; Xiaoming Chen 003; Michael T. Niemier; Xiaobo Sharon Hu (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Soft Error Mitigation for Deep Convolution Neural Network on FPGA Accelerators. - Wenshuo Li; Guangjun Ge; Kaiyuan Guo; Xiaoming Chen 003; Qi Wei 001; Zhen Gao 005; Yu Wang 002; Huazhong Yang (AICAS, 2020)

FTT-NAS: Discovering Fault-Tolerant Neural Architecture. - Wenshuo Li; Xuefei Ning; Guangjun Ge; Xiaoming Chen 003; Yu Wang 002; Huazhong Yang (ASP-DAC, 2020)

Search-free Accelerator for Sparse Convolutional Neural Networks. - Bosheng Liu; Xiaoming Chen 003; Yinhe Han 001; Ying Wang 001; Jiajun Li; Haobo Xu; Xiaowei Li 001 (ASP-DAC, 2020)

An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators. - Hanbo Sun; Zhenhua Zhu; Yi Cai 003; Xiaoming Chen 003; Yu Wang 002; Huazhong Yang (ASP-DAC, 2020)

Black Box Search Space Profiling for Accelerator-Aware Neural Architecture Search. - Shulin Zeng; Hanbo Sun; Yu Xing; Xuefei Ning; Yi Shan; Xiaoming Chen 003; Yu Wang 002; Huazhong Yang (ASP-DAC, 2020)

Dadu-CD: Fast and Efficient Processing-in-Memory Accelerator for Collision Detection. - Yuxin Yang 002; Xiaoming Chen 003; Yinhe Han 001 (DAC, 2020)

TUPIM: A Transparent and Universal Processing-in-Memory Architecture for Unmodified Binaries. - Sheng Xu; Xiaoming Chen 003; Xuehai Qian; Yinhe Han 001 (ACM Great Lakes Symposium on VLSI, 2020)

Accelerating RRT Motion Planning Using TCAM. - Yuxin Yang 002; Shiqi Lian; Xiaoming Chen 003; Yinhe Han 001 (ACM Great Lakes Symposium on VLSI, 2020)

MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems. - Zhenhua Zhu; Hanbo Sun; Kaizhong Qiu; Lixue Xia; Gokul Krishnan; Guohao Dai; Dimin Niu; Xiaoming Chen 003; Xiaobo Sharon Hu; Yu Cao 001; Yuan Xie 001; Yu Wang 002; et al. (ACM Great Lakes Symposium on VLSI, 2020)

Communication Lower Bound in Convolution Accelerators. - Xiaoming Chen 003; Yinhe Han 001; Yu Wang 002 (HPCA, 2020)

DaDu Series - Fast and Efficient Robot Accelerators. - Yinhe Han 001; Yuxin Yang 002; Xiaoming Chen 003; Shiqi Lian (ICCAD, 2020)

FTT-NAS: Discovering Fault-Tolerant Neural Architecture. - Xuefei Ning; Guangjun Ge; Wenshuo Li; Zhenhua Zhu; Yin Zheng; Xiaoming Chen 003; Zhen Gao 005; Yu Wang 002; Huazhong Yang (CoRR, 2020)

The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures. - Xiaoming Chen 003; Kai Ni 004; Michael T. Niemier; Dayane Reis; Xiaoyu Sun 001; Panni Wang; Suman Datta; Xiaobo Sharon Hu; Xunzhao Yin; Matthew Jerry; Shimeng Yu; Ann Franchesca Laguna (IEEE Des. Test, 2020)

Enabling Secure NVM-Based in-Memory Neural Network Computing by Sparse Fast Gradient Encryption. - Yi Cai 003; Xiaoming Chen 003; Lu Tian; Yu Wang 002; Huazhong Yang (IEEE Trans. Computers, 2020)

Long Live TIME: Improving Lifetime and Security for NVM-Based Training-in-Memory Systems. - Yi Cai 003; Yujun Lin 001; Lixue Xia; Xiaoming Chen 003; Song Han 003; Yu Wang 002; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Swallow: A Versatile Accelerator for Sparse Neural Networks. - Bosheng Liu; Xiaoming Chen 003; Yinhe Han 001; Haobo Xu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

FePIM: Contention-Free In-Memory Computing Based on Ferroelectric Field-Effect Transistors. - Xiaoming Chen 003; Yuping Wu; Yinhe Han 001 (ASP-DAC, 2021)

ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption. - Ning Lin; Xiaoming Chen 003; Chunwei Xia; Jing Ye 001; Xiaowei Li 001 (ATS, 2021)

F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM. - Bosheng Liu; Zhuoshen Jiang; Jigang Wu; Xiaoming Chen 003; Yinhe Han 001; Peng Liu 045 (DAC, 2021)

BRAHMS: Beyond Conventional RRAM-based Neural Network Accelerators Using Hybrid Analog Memory System. - Tao Song; Xiaoming Chen 003; Xiaoyu Zhang 009; Yinhe Han 001 (DAC, 2021)

Eliminating Iterations of Iterative Methods: Solving Large-Scale Sparse Linear System in O(1) with RRAM-based In-Memory Accelerator. - Tao Song; Xiaoming Chen 003; Yinhe Han 001 (ACM Great Lakes Symposium on VLSI, 2021)

CoPIM: A Concurrency-aware PIM Workload Offloading Architecture for Graph Applications. - Liang Yan; Mingzhe Zhang; Rujia Wang; Xiaoming Chen 003; Xingqi Zou; Xiaoyang Lu; Yinhe Han 001; Xian-He Sun (ISLPED, 2021)

RRAM-based Analog In-Memory Computing : Invited Paper. - Xiaoming Chen 003; Tao Song; Yinhe Han 001 (NANOARCH, 2021)

Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology. - Xingqi Zou; Sheng Xu; Xiaoming Chen 003; Liang Yan; Yinhe Han 001 (Sci. China Inf. Sci., 2021)

Chaotic Weights: A Novel Approach to Protect Intellectual Property of Deep Neural Networks. - Ning Lin; Xiaoming Chen 003; Hang Lu; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture. - Xuefei Ning; Guangjun Ge; Wenshuo Li; Zhenhua Zhu; Yin Zheng; Xiaoming Chen 003; Zhen Gao 005; Yu Wang 002; Huazhong Yang (ACM Trans. Design Autom. Electr. Syst., 2021)

Solving Least-Squares Fitting in $O(1)$ Using RRAM-based Computing-in-Memory Technique. - Xiaoming Chen 003; Yinhe Han 001 (ASP-DAC, 2022)

Optimal Data Allocation for Graph Processing in Processing-in-Memory Systems. - Zerun Li; Xiaoming Chen 003; Yinhe Han 001 (ASP-DAC, 2022)

FeMIC: Multi-Operands in-Memory Computing Based on FeFETs. - Rui Liu; Xiaoyu Zhang 009; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (ASP-DAC, 2022)

GraphRing: an HMC-ring based graph processing framework with optimized data movement. - Zerun Li; Xiaoming Chen 003; Yinhe Han 001 (DAC, 2022)

Energy-Efficient In-SRAM Accumulation for CMOS-based CNN Accelerators. - Wanqian Li; Yinhe Han 001; Xiaoming Chen 003 (ACM Great Lakes Symposium on VLSI, 2022)

P3S: A High Accuracy Probabilistic Prediction Processing System for CNN Acceleration. - Hang Xiao; Haobo Xu; Xiaoming Chen 003; Yujie Wang; Yinhe Han 001 (ACM Great Lakes Symposium on VLSI, 2022)

AIC-Bench: Workload Selection Methodology for Benchmarking AI Chips. - Zhenyu Quan; Xiaoming Chen 003; Yinhe Han 001 (HPCC/DSS/SmartCity/DependSys, 2022)

PME: Processing-in-memory Masking and Encoding for Secure NVM. - Zhiwen Xie; Yinhe Han 001; Xiaoming Chen 003 (HPCC/DSS/SmartCity/DependSys, 2022)

Numerically-Stable and Highly-Scalable Parallel LU Factorization for Circuit Simulation. - Xiaoming Chen 003 (ICCAD, 2022)

VNet: a versatile network to train real-time semantic segmentation models on a single GPU. - Wenxing Li; Ning Lin; Mingzhe Zhang; Hang Lu; Xiaoming Chen 003; Xiaowei Li 001 (Sci. China Inf. Sci., 2022)

Fast and High-Accuracy Approximate MAC Unit Design for CNN Computing. - Hang Xiao; Haobo Xu; Xiaoming Chen 003; Yujie Wang; Yinhe Han 001 (IEEE Embed. Syst. Lett., 2022)

Search-Free Inference Acceleration for Sparse Convolutional Neural Networks. - Bosheng Liu; Xiaoming Chen 003; Yinhe Han 001; Jigang Wu; Liang Chang 003; Peng Liu 045; Haobo Xu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory Architecture. - Xiaoyu Zhang 009; Rui Liu; Tao Song; Yuxin Yang 002; Yinhe Han 001; Xiaoming Chen 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Toward Efficient Computing for Robotics: From a Circuit and System View. - Haobo Xu; Yuxin Yang 002; Feng Min; Junpei Huang; Xiaoming Chen 003; Yinhe Han 001; Ninghui Sun (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-Sharing Approach. - Bosheng Liu; Hongyi Liang; Jigang Wu; Xiaoming Chen 003; Peng Liu 045; Yinhe Han 001 (ASP-DAC, 2023)

PIMCOMP: A Universal Compilation Framework for Crossbar-based PIM DNN Accelerators. - Xiaotian Sun; Xinyu Wang; Wanqian Li; Lei Wang 222; Yinhe Han 001; Xiaoming Chen 003 (DAC, 2023)

FSPA: An FeFET-based Sparse Matrix-Dense Vector Multiplication Accelerator. - Xiaoyu Zhang 009; Zerun Li; Rui Liu; Xiaoming Chen 003; Yinhe Han 001 (DAC, 2023)

Meltrix: A RRAM-Based Polymorphic Architecture Enhanced by Function Synthesis. - Boyu Long; Libo Shen; Xiaoyu Zhang 009; Yinhe Han 001; Xian-He Sun; Xiaoming Chen 003 (ICCAD, 2023)

LIM-GEN: A Data-Guided Framework for Automated Generation of Heterogeneous Logic-in-Memory Architecture. - Libo Shen; Boyu Long; Rui Liu; Xiaoyu Zhang 009; Yinhe Han 001; Xiaoming Chen 003 (ICCAD, 2023)

Hardware-Software Co-Design for Content-Based Sparse Attention. - Rui Tang; Xiaoyu Zhang 009; Rui Liu; Zhejian Luo; Xiaoming Chen 003; Yinhe Han 001 (ICCD, 2023)

Dadu-RBD: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines. - Yuxin Yang 002; Xiaoming Chen 003; Yinhe Han 001 (MICRO, 2023)

Resistive memory-based zero-shot liquid state machine for multimodal event data learning. - Ning Lin; Shaocong Wang; Yi Li 049; Bo Wang 153; Shuhui Shi; Yangu He; Woyu Zhang; Yifei Yu; Yue Zhang 011; Xiaojuan Qi 001; Xiaoming Chen 003; Hao Jiang 024; et al. (CoRR, 2023)

RBDCore: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines. - Yuxin Yang 002; Xiaoming Chen 003; Yinhe Han 001 (CoRR, 2023)

FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing. - Rui Liu; Xiaoyu Zhang 009; Zhiwen Xie; Xinyu Wang; Zerun Li; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures. - Zhenhua Zhu; Hanbo Sun; Tongxin Xie; Yu Zhu; Guohao Dai; Lixue Xia; Dimin Niu; Xiaoming Chen 003; Xiaobo Sharon Hu; Yu Cao 001; Yuan Xie 001; Huazhong Yang; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Frequency-Domain Inference Acceleration for Convolutional Neural Networks Using ReRAMs. - Bosheng Liu; Zhuoshen Jiang; Yalan Wu; Jigang Wu; Xiaoming Chen 003; Peng Liu 045; Qingguo Zhou; Yinhe Han 001 (IEEE Trans. Parallel Distributed Syst., 2023)

ACES: Accelerating Sparse Matrix Multiplication with Adaptive Execution Flow and Concurrency-Aware Cache Optimizations. - Xiaoyang Lu; Boyu Long; Xiaoming Chen 003; Yinhe Han 001; Xian-He Sun (ASPLOS (3), 2024)

ReCG: ReRAM-Accelerated Sparse Conjugate Gradient. - Mingjia Fan; Xiaoming Chen 003; Dechuang Yang; Zhou Jin 001; Weifeng Liu 002 (DAC, 2024)

Older and Wiser: The Marriage of Device Aging and Intellectual Property Protection of DNNs. - Ning Lin; Shaocong Wang; Yue Zhang 011; Yangu He; Kwunhang Wong; Arindam Basu; Dashan Shang; Xiaoming Chen 003; Zhongrui Wang (DAC, 2024)

PIMSYN: Synthesizing Processing-in-Memory CNN Accelerators. - Wanqian Li; Xiaotian Sun; Xinyu Wang; Lei Wang 222; Yinhe Han 001; Xiaoming Chen 003 (DATE, 2024)

PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators. - Xinyu Wang; Xiaotian Sun; Yinhe Han 001; Xiaoming Chen 003 (DATE, 2024)

LSMR: Synergy Randomness in Liquid State Machine and RRAM-based Analog-digital Accelerator. - Ning Lin; Songqi Wang; Xinyuan Zhang; Shaocong Wang; Yangu He; Woyu Zhang; Bo Wang 153; Jiankun Li; Mingzi Li; Binbin Cui; Yi Li 049; Jia Chen; et al. (ICCAD, 2024)

SNNGX: Securing Spiking Neural Networks with Genetic XOR Encryption on RRAM-based Neuromorphic Accelerator. - Kwunhang Wong; Songqi Wang; Wei Huang 042; Xinyuan Zhang; Yangu He; Karl Ming Him Lai; Yuzhong Jiao; Ning Lin; Xiaojuan Qi 001; Xiaoming Chen 003; Zhongrui Wang (ICCAD, 2024)

MemSort: In-Memory Sorting Architecture. - Rui Liu; Xiaoyu Zhang 009; Xinyu Wang; Feng Min; Zhejian Luo; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (ICCD, 2024)

AceMiner: Accelerating Graph Pattern Matching using PIM with Optimized Cache System. - Liang Yan; Xiaoyang Lu; Xiaoming Chen 003; Sheng Xu; Xingqi Zou; Yinhe Han 001; Xian-He Sun (ICCD, 2024)

Accelerating Frequency-domain Convolutional Neural Networks Inference using FPGAs. - Yi Chen; Bosheng Liu; Yongqi Xu; Jigang Wu; Xiaoming Chen 003; Peng Liu 045; Qingguo Zhou; Yinhe Han 001 (ISCAS, 2024)

TMiner: A Vertex-Based Task Scheduling Architecture for Graph Pattern Mining. - Zerun Li; Xiaoming Chen 003; Yinhe Han 001 (MICRO, 2024)

JANM-IK: Jacobian Argumented Nelder-Mead Algorithm for Inverse Kinematics and its Hardware Acceleration. - Yuxin Yang 002; Xiaoming Chen 003; Yinhe Han 001 (IEEE Comput. Archit. Lett., 2024)

Older and Wiser: The Marriage of Device Aging and Intellectual Property Protection of Deep Neural Networks. - Ning Lin; Shaocong Wang; Yue Zhang 011; Yangu He; Kwunhang Wong; Arindam Basu; Dashan Shang; Xiaoming Chen 003; Zhongrui Wang (CoRR, 2024)

BitQ: Tailoring Block Floating Point Precision for Improved DNN Efficiency on Resource-Constrained Devices. - Yongqi Xu; Yujian Lee; Gao Yi; Bosheng Liu; Yucong Chen; Peng Liu 045; Jigang Wu; Xiaoming Chen 003; Yinhe Han 001 (CoRR, 2024)

Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators. - Wanqian Li; Yinhe Han 001; Xiaoming Chen 003 (ACM Trans. Design Autom. Electr. Syst., 2024)

GAS: General-Purpose In-Memory-Computing Accelerator for Sparse Matrix Multiplication. - Xiaoyu Zhang 009; Zerun Li; Rui Liu; Xiaoming Chen 003; Yinhe Han 001 (IEEE Trans. Computers, 2024)

Crypto-DSEDA: A Domain-Specific EDA Flow for CiM-Based Cryptographic Accelerators. - Rui Liu; Zerun Li; Xiaoyu Zhang 009; Wanqian Li; Libo Shen; Rui Tang; Zhejian Luo; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (IEEE Des. Test, 2024)

Concurrency-Aware Cache Miss Cost Prediction with Perceptron Learning. - Yuping Wu; Xiaoyang Lu; Xiaoming Chen 003; Yinhe Han 001; Xian-He Sun (ACM Great Lakes Symposium on VLSI, 2025)

In-Memory Computing Accelerator for Iterative Linear Algebra Solvers. - Rui Liu; Zerun Li; Xiaoyu Zhang 009; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (IEEE Comput. Archit. Lett., 2025)

Pyramid: Accelerating LLM Inference With Cross-Level Processing-in-Memory. - Liang Yan; Xiaoyang Lu; Xiaoming Chen 003; Yinhe Han 001; Xian-He Sun (IEEE Comput. Archit. Lett., 2025)

Resistive memory-based zero-shot liquid state machine for multimodal event data learning. - Ning Lin; Shaocong Wang; Yi Li 049; Bo Wang 153; Shuhui Shi; Yangu He; Woyu Zhang; Yifei Yu; Yue Zhang 011; Xinyuan Zhang; Kwunhang Wong; Songqi Wang; et al. (Nat. Comput. Sci., 2025)

A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing. - Zerun Li; Xiaoming Chen 003; Yuxin Yang 002; Feng Min; Xiaoyu Zhang 009; Yinhe Han 001 (IEEE Trans. Computers, 2025)

Identifying Optimal Workload Offloading Partitions for CPU-PIM Graph Processing Accelerators. - Sheng Xu; Chun Li; Le Luo 002; Wu Zhou; Liang Yan; Xiaoming Chen 003 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations. - Xiaoming Chen 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators. - Xiaotian Sun; Xinyu Wang; Wanqian Li; Yinhe Han 001; Xiaoming Chen 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Re-Meltrix: A Reconfigurable Processing-in-Memory Architecture Based on RRAM and Function Synthesis. - Boyu Long; Yinhe Han 001; Xian-He Sun; Xiaoming Chen 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)