Reconfigurable Cipher Processing Framework and Implementation. - Jingfei Jiang; Xiaoqiang Ni; Minxuan Zhang (APPT, 2003)

A New Computer Architecture Using a New Program Driving Method. - Xiaobo Li; Xiangdong Cui; Xiaoqiang Ni; Chiyuan Ma; Jingfei Jiang; Huiping Zhou; Zhou Zhou; Ke Luo; Jiangsha Deng (ACIS-ICIS, 2006)

A New Processor Architecture with a New Program Driving Method. - Xiaobo Li; Ke Luo; Xiangdong Cui; Lalin Jiang; Xiaoqiang Ni; Chiyuan Ma; Jingfei Jiang; Huiping Zhou; Zhou Zhou (CDES, 2006)

Performance Optimization Strategies of High Performance Computing on GPU. - Anguo Ma; Jing Cai; Yu Cheng; Xiaoqiang Ni; Yuxing Tang; Zuocheng Xing (APPT, 2009)

A memory schedule policy oriented to stream architecture. - Chiyuan Ma; Xiaoqiang Ni (RTCSA, 2014)

The Macro-DSE for HPC Processing Unit: The Physical Constraints Perspective. - Yuxing Tang; Lei Wang 011; Yu Deng 001; Xiaoqiang Ni; Qiang Dou (GPC, 2016)

Language-Extension-Based Vectorizing Compiling Scheme on SDR-DSP. - Xiaoqiang Ni; Liu Yang; Chiyuan Ma (NCCET, 2016)

Research of Configurable Hybrid Memory Architecture for Big Data Processing. - Hongwei Zhou; Rangyu Deng; Quanyou Feng; Xiaoqiang Ni; Qiang Dou (NCCET, 2017)

Traversal Packets: Opportunistic Bypass Packets for Deadlock Recovery. - Zhiqiang Chen; Rangyu Deng; Kun Zeng; Xiaoqiang Ni; Hongwei Zhou (IEEE Des. Test, 2022)