An optimized delay-aware common subexpression elimination algorithm for hardware implementation of binary-field linear transform. - Xiaoqiang Zhang 001; Ning Wu; Fang Zhou 001; Xin Chen 039 (IEICE Electron. Express, 2014)

An evolutionary algorithm based on novel hybrid repair strategy for combinational logic circuits. - Xinjie Huang; Ning Wu; Xiaoqiang Zhang 001; Yaoping Liu (IEICE Electron. Express, 2015)

High-performance adaptive hybrid wireless NoC architecture based on improved congestion measurement. - Jianhua Li; Ning Wu; Yongliang Hu; Xiaoqiang Zhang 001 (IEICE Electron. Express, 2015)

Low-delay parallel Chien search architecture for RS decoder. - Xiaoqiang Zhang 001; Ning Wu; Fang Zhou 001; Jianhua Li; Yasir Khizar (IEICE Electron. Express, 2016)

Against fault attacks based on random infection mechanism. - Jinbao Zhang 002; Ning Wu; Xiaoqiang Zhang 001; Fang Zhou 001 (IEICE Electron. Express, 2016)

Optimization of Area and Delay for Implementation of the Composite Field Advanced Encryption Standard S-Box. - Xiaoqiang Zhang 001; Ning Wu; Fang Zhou 001; Fen Ge (J. Circuits Syst. Comput., 2016)

A new compact hardware architecture of S-Box for block ciphers AES and SM4. - Yaoping Liu; Ning Wu; Xiaoqiang Zhang 001; Fang Zhou 001 (IEICE Electron. Express, 2017)

FPGA based highly efficient MISTY1 architecture. - Yasir Khizar; Ning Wu; Xin Chen 039; Muhammad Rehan Yahya; Xiaoqiang Zhang 001 (IEICE Electron. Express, 2017)

Research on physical unclonable functions circuit based on three dimensional integrated circuit. - Tianming Ni; Hao Chang; Xiaoqiang Zhang 001; Hao Xiao; Zhengfeng Huang (IEICE Electron. Express, 2018)

High performance AES-GCM implementation based on efficient AES and FR-KOA multiplier. - Yong Zhang; Ning Wu; Fang Zhou 001; Xiaoqiang Zhang 001; Jinbao Zhang 002 (IEICE Electron. Express, 2018)

Compact Hardware Implementations of MISTY1 Block Cipher. - Yasir Khizar; Ning Wu; Xiaoqiang Zhang 001 (J. Circuits Syst. Comput., 2018)

An Optimized Design for Compact Masked AES S-Box Based on Composite Field and Common Subexpression Elimination Algorithm. - Yunfei Ye; Ning Wu; Xiaoqiang Zhang 001; Liling Dong; Fang Zhou 001 (J. Circuits Syst. Comput., 2018)

Poet: A Power Efficient Hybrid Optical NoC Topology for Heterogeneous CPU-GPU Systems. - Tao Cheng; Ning Wu; Gaizhen Yan; Xinggan Zhang; Xiaoqiang Zhang 001 (IECON, 2019)

A new method for resisting collision attack based on parallel random delay S-box. - Fang Zhou 001; Ning Wu; Xiaoqiang Zhang 001; Jinbao Zhang 002 (IEICE Electron. Express, 2019)

A full matrix joint optimization method for hardware implementation of AES MixColumns/InvMixColumns. - Xiaoqiang Zhang 001; Fan Yang; Xinxing Zheng; Xinggan Zhang; Ning Wu (IEICE Electron. Express, 2020)

A low critical path delay structure for composite field AES S-box based on constant matrices multiplication merging. - Xiaoqiang Zhang 001; Xinggan Zhang; Lan Tang; Xinxing Zheng; Tianming Ni; Ning Wu (IEICE Electron. Express, 2020)

A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology. - Tianming Ni; Zhao Yang; Hao Chang; Xiaoqiang Zhang 001; Lin Lu; Aibin Yan; Zhengfeng Huang; Xiaoqing Wen (IEEE Trans. Emerg. Top. Comput., 2021)

Low delay AES S-box designs based on matrix merging method. - Xiaoqiang Zhang 001; Lan Tang; Xinggan Zhang; Xinxing Zheng; Mingyu Xu; Fan Yang (IEICE Electron. Express, 2022)