A switched mode Li-ion battery charger with multiple energy harvesting systems simultaneously used as input sources. - Judy M. Amanor-Boadu; Mohamed A. Abouzied; Salvador Carreon-Bautista; Roland Ribeiro; Xiaosen Liu; Edgar Sánchez-Sinencio (MWSCAS, 2014)

SmartShelter: A Sustainable power system design using energy harvesting techniques. - Leticia Ibarra; Benjamin Hilton; Mehna Nawal; Salvador Carreon-Bautista; Mohamed Abouzied; Xiaosen Liu; Roland Ribeiro; Judy Amanor-Badu; Ethan Miller; Jorge Vanegas; Edgar Sánchez-Sinencio (MWSCAS, 2014)

20.7 A 0.45-to-3V reconfigurable charge-pump energy harvester with two-dimensional MPPT for Internet of Things. - Xiaosen Liu; Edgar Sánchez-Sinencio (ISSCC, 2015)

An 86% Efficiency 12 µW Self-Sustaining PV Energy Harvesting System With Hysteresis Regulation and Time-Domain MPPT for IOT Smart Nodes. - Xiaosen Liu; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2015)

An Automatic Resonance Tracking Scheme With Maximum Power Transfer for Piezoelectric Transducers. - Xiaosen Liu; Adrian Colli-Menchi; James G. R. Gilbert; Daniel A. Friedrichs; Keith Malang; Edgar Sánchez-Sinencio (IEEE Trans. Ind. Electron., 2015)

A Highly Efficient Ultralow Photovoltaic Power Harvesting System With MPPT for Internet of Things Smart Nodes. - Xiaosen Liu; Edgar Sánchez-Sinencio (IEEE Trans. Very Large Scale Integr. Syst., 2015)

21.1 A single-cycle MPPT charge-pump energy harvester using a thyristor-based VCO without storage capacitor. - Xiaosen Liu; Edgar Sánchez-Sinencio (ISSCC, 2016)

A Highly Efficient Reconfigurable Charge Pump Energy Harvester With Wide Harvesting Range and Two-Dimensional MPPT for Internet of Things. - Xiaosen Liu; Lilly Huang; Krishnan Ravichandran; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2016)

21.4 A reduced-order sliding-mode controller with an auxiliary PLL frequency discriminator for ultrasonic electric scalpels. - Xiaosen Liu; Adrian I. Colli-Menchi; Edgar Sánchez-Sinencio (ISSCC, 2017)

Ultrasonic Electric Scalpels Based on a Sliding-Mode Controller With an Auxiliary PLL Frequency Discriminator. - Xiaosen Liu; Adrian I. Colli-Menchi; Edgar Sánchez-Sinencio (IEEE Trans. Biomed. Circuits Syst., 2017)

A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes. - Suhwan Kim 002; Vaibhav A. Vaidya; Christopher Schaef; Andrew Lines; Harish Krishnamurthy; Sheldon Weng; Xiaosen Liu; Dileep Kurian; Tanay Karnik; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2018)

A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS. - Harish Kumar Krishnamurthy; Vaibhav A. Vaidya; Pavan Kumar 001; Rinkle Jain; Sheldon Weng; Stephen T. Kim; George E. Matthew; Nachiket V. Desai; Xiaosen Liu; Krishnan Ravichandran; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2018)

A Switched Capacitor Energy Harvester Based on a Single-Cycle Criterion for MPPT to Eliminate Storage Capacitor. - Xiaosen Liu; Krishnan Ravichandran; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation. - Xiaosen Liu; Harish K. Krishnamurthy; Taesik Na; Sheldon Weng; Khondker Zakir Ahmed 001; Krishnan Ravichandran; James W. Tschanz; Vivek De (ISSCC, 2019)

A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response. - Zakir K. Ahmed 001; Harish K. Krishnamurthy; Charles Augustine; Xiaosen Liu; Sheldon Weng; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2019)

A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors. - Christopher Schaef; Kaladhar Radhakrishnan; Krishnan Ravichandran; James W. Tschanz; Vivek De; Nachiket V. Desai; Harish K. Krishnamurthy; Xiaosen Liu; Khondker Zakir Ahmed 001; Suhwan Kim 002; Sheldon Weng; Huong T. Do; et al. (IEEE J. Solid State Circuits, 2019)

Digital Control of Switching and Linear Integrated Voltage Regulators. - Harish K. Krishnamurthy; Zakir A. Khondker 001; Xiaosen Liu; Nachiket V. Desai; Suhwan Kim 002; Nicolas Butzen; Sally Amin; Sheldon Weng; Krishnan Ravichandran; James W. Tschanz; Vivek De (CICC, 2020)

An Autonomous Reconfigurable Power Delivery Network (RPDN) for Many-Core SoCs Featuring Dynamic Current Steering. - Zakir K. Ahmed 001; Harish K. Krishnamurthy; Sheldon Weng; Xiaosen Liu; Christopher Schaef; Nachiket V. Desai; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2020)

A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures. - Raghavan Kumar; Xiaosen Liu; Vikram B. Suresh; Harish Krishnamurthy; Mark A. Anders 001; Himanshu Kaul; Krishnan Ravichandran; Vivek De; Sanu Mathew (VLSI Circuits, 2020)

A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency. - Xiaosen Liu; Harish K. Krishnamurthy; Claudia P. Barrera; Jing Han; Rajasekhara M. Narayana Bhatla; Scott Chiu; Zakir K. Ahmed 001; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2020)

A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response. - Khondker Zakir Ahmed 001; Harish K. Krishnamurthy; Charles Augustine; Xiaosen Liu; Sheldon Weng; Krishnan Ravichandran; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2020)

17.4 Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing. - Nachiket V. Desai; Harish K. Krishnamurthy; Khondker Zakir Ahmed 001; Sheldon Weng; Suhwan Kim 002; Xiaosen Liu; Huong T. Do; Kaladhar Radhakrishnan; Krishnan Ravichandran; James W. Tschanz; Vivek De (ISSCC, 2021)

A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction. - Khondker Zakir Ahmed 001; Nachiket V. Desai; Harish K. Krishnamurthy; Sheldon Weng; Xiaosen Liu; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2021)

A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS. - Raghavan Kumar; Xiaosen Liu; Vikram B. Suresh; Harish K. Krishnamurthy; Sudhir Satpathy; Mark A. Anders 001; Himanshu Kaul; Krishnan Ravichandran; Vivek De; Sanu K. Mathew (IEEE J. Solid State Circuits, 2021)

A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning. - Xiaosen Liu; Harish K. Krishnamurthy; Taesik Na; Sheldon Weng; Khondker Zakir Ahmed 001; Christopher Schaef; Krishnan Ravichandran; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2021)

Recent Advances on Linear Low-Dropout Regulators. - José Silva-Martínez; Xiaosen Liu; Dadian Zhou (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer. - Xiaosen Liu; Harish Krishnamurthy; Renzhi Liu; Krishnan Ravichandran; Zakir K. Ahmed 001; Nachiket V. Desai; Nicolas Butzen; James W. Tschanz; Vivek De (ISSCC, 2022)

A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference. - Hechen Wang; Renzhi Liu; Richard Dorrance; Deepak Dasalukunte; Xiaosen Liu; Dan Lake; Brent R. Carlton; May Wu (VLSI Technology and Circuits, 2022)

EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation. - Debayan Das; Mayukh Nath; Baibhab Chatterjee; Raghavan Kumar; Xiaosen Liu; Harish Krishnamurthy; Manoj R. Sastry; Sanu Mathew; Santosh Ghosh; Shreyas Sen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Fast Surrogate-Assisted Constrained Multiobjective Optimization for Analog Circuit Sizing via Self-Adaptive Incremental Learning. - Sen Yin; Ruitao Wang; Jian Zhang 085; Xiaosen Liu; Yan Wang 023 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads. - Xuliang Wang; Xiaosen Liu; Wing-Hung Ki (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Methods of Reducing the Intrinsic Loss for Continuously-Scalable-Conversion-Ratio SC Converters. - Yongjuan Shi; Chen Hu; Xiaosen Liu; Xun Liu; Junmin Jiang (APCCAS, 2024)

An Efficient Transfer Learning Assisted Global Optimization Scheme for Analog/RF Circuits. - Zhikai Wang; Jingbo Zhou; Xiaosen Liu; Yan Wang 023 (ASPDAC, 2024)

A 92%-Efficiency 0.828μs Settling Time FC5L Voltage Regulator Featuring Time-Domain Charge Balancing & Flying Capacitor Self-Switching for Wide Dynamic Range & Fast Transient Chiplet Applications. - Xichen Sun; Jingshu Yu; Xuliang Wang; Jin Wei; Junmin Jiang; Chenchang Zhan; Yan Wang 023; Xiaosen Liu (CICC, 2024)

A Two-step Fine-tuning Assisted Layout Sizing Scheme for Analog/RF Circuits. - Zhikai Wang; Zuochang Ye; Jingbo Zhou; Xiaosen Liu; Yan Wang 023 (ISCAS, 2024)

31.7 A 3.6W 16V-Output 180ns-Response-Time 94%-Efficiency SC Sigma Converter with Output Impedance Compensation and Ripple Mitigation for LiDAR Driver Applications. - Chen Hu; Xinran Huang; Xun Liu; Sijun Du; Xiaosen Liu; Junmin Jiang (ISSCC, 2024)

14.9 A Monolithic 10.5W/mm2600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS. - Suhwan Kim 002; Harish K. Krishnamurthy; Zakir K. Ahmed 001; Nachiket V. Desai; Sheldon Weng; Anne Augustine; Huong T. Do; Jingshu Yu; Phong D. Bach; Xiaosen Liu; Kaladhar Radhakrishnan; Krishnan Ravichandran; et al. (ISSCC, 2024)

A Monolithic 5.7A/mm2 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs. - Jingshu Yu; Xiaosen Liu; Minxiang Gong; Nicolas Butzen; Sheldon Weng; Harish K. Krishnamurthy; Krishnan Ravichandran; Ramez Hosseinian Ahangharnejhad; Jim Waldemer; Christopher Pelto; James W. Tschanz; Vivek De (VLSI Technology and Circuits, 2024)

Automatic Design for W-Band Front-End System via Bottom-Up Sizing and Layout Generation. - Sen Yin; Ruitao Wang; Jian Zhang 085; Xiaosen Liu; Yan Wang 023 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

3D-IC Chiplet Integrated Power Supply with LDO, SCVR, and Buck DC-DC Converter. - Xiaosen Liu; Xichen Sun; Haozhe Zhang; Yan Wang 023 (CICC, 2025)

A 6.87W 3.7-5V Input 12.6-24V Output Switched-Capacitor Sigma Converter with Multiple Voltage Domains. - Lingfeng Zhu; Chen Hu; Wing-Hung Ki; Xun Liu; Xiaosen Liu; Junmin Jiang (CICC, 2025)

A Monolithic, 10.5 W/mm2, 600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16 nm Class. - Suhwan Kim 002; Harish K. Krishnamurthy; Zakir K. Ahmed 001; Nachiket V. Desai; Sheldon Weng; Anne Augustine; Huong T. Do; Jingshu Yu; Phong D. Bach; Xiaosen Liu; Kaladhar Radhakrishnan; Krishnan Ravichandran; et al. (IEEE J. Solid State Circuits, 2025)

A Monolithic 5.7 A/mm2 91% Peak Efficiency Scalable Multistage Modular Switched Capacitor Voltage Regulator for Base Die Vertical Power Delivery in 3D-ICs. - Xiaosen Liu; Jingshu Yu; Minxiang Gong; Nicolas Butzen; Sheldon Weng; Harish K. Krishnamurthy; Krishnan Ravichandran; Ramez Hosseinian Ahangharnejhad; James Waldemer; Christopher Pelto; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2025)