MCFRoute: a detailed router based on multi-commodity flow method. - Xiaotao Jia; Yici Cai; Qiang Zhou 001; Gang Chen; Zhuoyuan Li 003; Zuowei Li (ICCAD, 2014)

A New Random-Walk Based Label Propagation Community Detection Algorithm. - Chang Su 003; Xiaotao Jia; Xianzhong Xie; Yue Yu (WI-IAT (1), 2015)

MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router. - Xiaotao Jia; Yici Cai; Qiang Zhou 001; Bei Yu 001 (ACM Great Lakes Symposium on VLSI, 2016)

Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers. - Xueyan Wang; Xiaotao Jia; Qiang Zhou 001; Yici Cai; Jianlei Yang 001; Mingze Gao; Gang Qu 001 (ACM Great Lakes Symposium on VLSI, 2016)

Spintronics based stochastic computing for efficient Bayesian inference system. - Xiaotao Jia; Jianlei Yang 001; Zhaohao Wang; Yiran Chen 001; Hai Helen Li; Weisheng Zhao (ASP-DAC, 2018)

Electromigration Design Rule aware Global and Detailed Routing Algorithm. - Xiaotao Jia; Jing Wang 224; Yici Cai; Qiang Zhou 001 (ACM Great Lakes Symposium on VLSI, 2018)

A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques. - Xiaotao Jia; Yici Cai; Qiang Zhou 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration. - Yinglin Zhao; Jianlei Yang 001; Xiaotao Jia; Xueyan Wang; Zhaohao Wang; Wang Kang 001; Youguang Zhang; Weisheng Zhao (ISVLSI, 2019)

TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. - Xueyan Wang; Jianlei Yang 001; Yinglin Zhao; Yingjie Qi; Meichen Liu; Xingzhou Cheng; Xiaotao Jia; Xiaoming Chen; Gang Qu 001; Weisheng Zhao (DAC, 2020)

MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique. - Zhen Zhuang; Genggeng Liu; Xing Huang 001; Xiaotao Jia; Wen-Hao Liu 001; Wenzhong Guo (ACM Great Lakes Symposium on VLSI, 2020)

An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing. - Yu Pan; Xiaotao Jia; Zhen Cheng; Peng Ouyang; Xueyan Wang; Jianlei Yang 001; Weisheng Zhao (CCF Trans. High Perform. Comput., 2020)

Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques. - Xueyan Wang; Jianlei Yang 001; Yinglin Zhao; Xiaotao Jia; Gang Qu 001; Weisheng Zhao (ACM J. Emerg. Technol. Comput. Syst., 2020)

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing. - Xiaotao Jia; Jianlei Yang 001; Pengcheng Dai; Runze Liu 001; Yiran Chen 001; Weisheng Zhao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. - Xiaotao Jia; Jianlei Yang 001; Runze Liu 001; Xueyan Wang; Sorin Dan Cotofana; Weisheng Zhao (IEEE Trans. Neural Networks Learn. Syst., 2021)

Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture. - Xueyan Wang; Jianlei Yang 001; Yinglin Zhao; Xiaotao Jia; Rong Yin 001; Xuhang Chen 001; Gang Qu 001; Weisheng Zhao (IEEE Trans. Computers, 2022)

Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture. - Xuhang Chen 001; Xueyan Wang; Xiaotao Jia; Jianlei Yang 001; Gang Qu 001; Weisheng Zhao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

" "Peak " Quantization: A Training Method Suitable for Terminal Equipment to Deploy Keyword Spotting Network". - Xiaomeng Luo; Guangcun Wei; Yuhao Liu; Xiaotao Jia; Xinghua Yang; Junlin Li; Qi Wei 001; Fei Qiao (ICAICE, 2023)

NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration. - Yinglin Zhao; Jianlei Yang 001; Bing Li; Xingzhou Cheng; Xucheng Ye; Xueyan Wang; Xiaotao Jia; Zhaohao Wang; Youguang Zhang; Weisheng Zhao (Sci. China Inf. Sci., 2023)

IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations. - Yuntao Wei; Xueyan Wang; Shangtong Zhang; Jianlei Yang 001; Xiaotao Jia; Zhaohao Wang; Gang Qu 001; Weisheng Zhao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. - Cenlin Duan; Jianlei Yang 001; Yiou Wang; Yikun Wang; Yingjie Qi; Xiaolin He; Bonan Yan; Xueyan Wang; Xiaotao Jia; Weisheng Zhao (DAC, 2024)

Hierarchical Placement Algorithm for Analog Circuit With Polygonal Modules. - Mengzhe Han; Xiaotao Jia; Zihao Zhao; Yingchun Hu (ISCAS, 2024)

Miniaturized and Integrated On-Chip Ag/AgCl Micro-electrodes for Chemical Detection. - Jing Liang; Xiaotao Jia; Yuanqi Hu (ISCAS, 2024)

LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators. - Yicheng Huang; Xueyan Wang; Tianao Dai; Jianlei Yang 001; Zhaojun Lu; Xiaotao Jia; Gang Qu 001; Weisheng Zhao (ITC-Asia, 2024)

CiM-BNN:Computing-in-MRAM Architecture for Stochastic Computing Based Bayesian Neural Network. - Huiyi Gu; Xiaotao Jia; Yuhao Liu; Jianlei Yang 001; Xueyan Wang; Youguang Zhang; Sorin Dan Cotofana; Weisheng Zhao (IEEE Trans. Emerg. Top. Comput., 2024)

DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. - Cenlin Duan; Jianlei Yang 001; Xiaolin He; Yingjie Qi; Yikun Wang; Yiou Wang; Ziyan He; Bonan Yan; Xueyan Wang; Xiaotao Jia; Weitao Pan; Weisheng Zhao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method. - Xiaotao Jia; Huiyi Gu; Yuhao Liu; Jianlei Yang 001; Xueyan Wang; Weitao Pan; Youguang Zhang; Sorin Cotofana; Weisheng Zhao (IEEE Trans. Neural Networks Learn. Syst., 2024)

MBQ: Modality-Balanced Quantization for Large Vision-Language Models. - Shiyao Li; Yingchun Hu; Xuefei Ning; Xihui Liu; Ke Hong; Xiaotao Jia; Xiuhong Li; Yaqi Yan; Pei Ran; Guohao Dai; Shengen Yan; Huazhong Yang; et al. (CVPR, 2025)

Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design. - Tianwei Pan; Tianao Dai; Jianlei Yang 001; Hongbin Jing; Yang Su; Zeyu Hao; Xiaotao Jia; Chunming Hu; Weisheng Zhao (ISCA, 2025)

Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity. - Cenlin Duan; Jianlei Yang 001; Yikun Wang; Yiou Wang; Yingjie Qi; Xiaolin He; Bonan Yan; Xueyan Wang; Xiaotao Jia; Weisheng Zhao (CoRR, 2025)