A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (APCCAS, 2019)

A 0.0018-mm2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter. - Xinyi Ge; Yong Chen 005; Xiaoteng Zhao; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (CICC, 2020)

A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme. - Lin Wang 115; Yong Chen 005; Chaowei Yang; Xiaoteng Zhao; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (ICECS 2022, 2022)

A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Lin Wang 115; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A 0.012mm2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply. - Zhicheng Dong; Shubin Liu; Xiaoteng Zhao; Baotian Hao; Hongzhi Liang; Haolin Han; Menghao Wang; Weijie Han; Zhangming Zhu (CICC, 2023)

A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique. - Lin Wang 115; Yong Chen 005; Chaowei Yang; Xiaoteng Zhao; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 0.0006-mm2 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS. - Zhicheng Dong; Xiaoteng Zhao; Zekai Yang; Xianting Su; Haolin Han; Feng Bu; Rong Zhou; Depeng Sun; Yong Chen 005; Shubin Liu; Ruixue Ding; Zhangming Zhu (A-SSCC, 2024)

A 0.9-V Supply Up to 21.5-dB Boost Gain Analog Front-End with T-coilloaded CTLE and VGA in 28-nm CMOS for 112-Gb/s PAM-4 Medium-Reach Receivers. - Miao Zhang; Xianting Su; Zekai Yang; Zhicheng Dong; Weitan Huang; Menghao Wang; Yukui Yu; Xiaoteng Zhao; Shubin Liu; Zhangming Zhu (ICTA, 2024)

A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm2 Area. - Zhicheng Dong; Xiaoteng Zhao; Weitan Huang; Yuan Gao; Depeng Sun; Shubin Liu; Lihong Yang; Zhangming Zhu (ISCAS, 2024)

A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS. - Shubin Liu; Chenxi Han; Xiaoteng Zhao; Yuhao Zhang; Shixin Li; Hongzhi Liang; Lihong Yang; Zhangming Zhu (Sci. China Inf. Sci., 2024)

A low-noise, 0.05-17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators. - Depeng Sun; Ruiqing Wang; Feng Bu; Yuan Gao; Xiaoteng Zhao; Ruixue Ding; Shubin Liu; Rong Zhou (Microelectron. J., 2024)

A 8.1-nW, 4.22-kHz, -40-85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications. - Rong Zhou; Linwei Wang; Jianhang Yang; Zhen Li; Xiaoteng Zhao; Shubin Liu (Microelectron. J., 2024)

A wideband low power RF Receiver Front-End for Internet-of-Things applications. - Rong Zhou; Jianhang Yang; Linwei Wang; Xiaoteng Zhao; Shubin Liu; Depeng Sun (Microelectron. J., 2024)

A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fsrms Integrated Jitter and -250.8-dB FOMPLL. - Depeng Sun; Linguo Huang; Rong Zhou; Feng Bu; Lisheng Chen; Xiaoteng Zhao; Ruixue Ding; Shubin Liu; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor. - Zhicheng Dong; Shubin Liu; Xiaoteng Zhao; Baotian Hao; Xianting Su; Hongzhi Liang; Menghao Wang; Zhangming Zhu (IEEE J. Solid State Circuits, 2024)

A 100Gb/s Transmitter with Digital Pre-Distortion and MUX-Merged Voltage-Mode Driver Achieving 3-Times INLPP Improvement in 28nm CMOS. - Chenxi Han; Xiaoteng Zhao; Qi Zhang; Yuan Liu; Yuhao Zhang; Hongzhi Liang; Yukui Yu; Shubin Liu; Zhangming Zhu (CICC, 2025)

A Reference-Less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed. - Xiaoteng Zhao; Yuhao Zhang; Hao Chang; Yilong Dong; Chenxi Han; Zekai Yang; Zhicheng Dong; Rong Zhou; Shubin Liu; Zhangming Zhu (ISSCC, 2025)

A 1-V 3.9-5.2-GHz reference-sampling PLL with 168-fsrms integrated jitter and -76-dBc reference spur. - Feng Bu; Ruixue Ding; Depeng Sun; Yuan Gao; Ruiqing Wang; Xiaoteng Zhao; Rong Zhou; Shubin Liu (Microelectron. J., 2025)

A 7.4-9.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration. - Feng Bu; Ruixue Ding; Depeng Sun; Ge Wang; Yuan Gao; Rong Zhou; Xiaoteng Zhao; Lisheng Chen; Shubin Liu; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2025)