Exploiting BIST Approach for Two-Pattern Testing. - Xiaowei Li 001; Paul Y. S. Cheung (Asian Test Symposium, 1998)

High-Level BIST Synthesis for Delay Testing. - Xiaowei Li 001; Paul Y. S. Cheung (DFT, 1998)

Data Path Synthesis for BIST with Low Area Overhead. - Xiaowei Li 001; Paul Y. S. Cheung (ASP-DAC, 1999)

Exploiting Test Resource Optimization in Data Path Synthesis for BIST. - Xiaowei Li 001; Paul Y. S. Cheung (Great Lakes Symposium on VLSI, 1999)

An approach to behavioral synthesis for loop-based BIST. - Xiaowei Li 001; Paul Y. S. Cheung (ISCAS (6), 1999)

Strong self-testability for data paths high-level synthesis. - Xiaowei Li 001; Toshimitsu Masuzawa; Hideo Fujiwara (Asian Test Symposium, 2000)

LFSR-Based Deterministic TPG for Two-Pattern Testing. - Xiaowei Li 001; Paul Y. S. Cheung; Hideo Fujiwara (J. Electron. Test., 2000)

High Level Synthesis for Loop-Based BIST. - Xiaowei Li 001; Paul Y. S. Cheung (J. Comput. Sci. Technol., 2000)

Exploiting Deterministic TPG for Path Delay Testing. - Xiaowei Li 001; Paul Y. S. Cheung (J. Comput. Sci. Technol., 2000)

An Approach to RTL Fault Extraction and Test Generation. - Zhigang Yin; Yinghua Min; Xiaowei Li 001 (Asian Test Symposium, 2001)

Reducing Power Dissipation during At-Speed Test Application. - Xiaowei Li 001; Huawei Li 001; Yinghua Min (DFT, 2001)

A Loop-Based Apparatus for At-Speed Self-Testing. - Xiaowei Li 001; Paul Y. S. Cheung (J. Comput. Sci. Technol., 2001)

Test Power Optimization Techniques for CMOS Circuits. - Zuying Luo; Xiaowei Li 001; Huawei Li 001; Shiyuan Yang; Yinghua Min (Asian Test Symposium, 2002)

The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications. - Zuying Luo; Yinghua Min; Shiyuan Yang; Xiaowei Li 001 (Sci. China Ser. F Inf. Sci., 2002)

An Expression's Single Fault Model and the Testing Methods. - Yunzhan Gong; Wanli Xu; Xiaowei Li 001 (Asian Test Symposium, 2003)

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. - Yinhe Han 001; Yongjun Xu 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (Asian Test Symposium, 2003)

Design Error Diagnosis Based on Verification Techniques. - Guanghui Li 001; Ming Shao; Xiaowei Li 001 (Asian Test Symposium, 2003)

Delay Test Pattern Generation Considering Crosstalk-Induced Effects. - Huawei Li 001; Yue Zhang; Xiaowei Li 001 (Asian Test Symposium, 2003)

An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains. - Tao Lv 001; Jianping Fan 002; Xiaowei Li 001 (Asian Test Symposium, 2003)

SAT-Based Algorithm of Verification for Port Order Fault. - Ming Shao; Guanghui Li 001; Xiaowei Li 001 (Asian Test Symposium, 2003)

Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits. - Yongjun Xu 001; Zuying Luo; Zhiguo Chen; Xiaowei Li 001 (Asian Test Symposium, 2003)

A Novel RT-Level Behavioral Description Based ATPG Method. - Zhigang Yin; Yinghua Min; Xiaowei Li 001; Huawei Li 001 (J. Comput. Sci. Technol., 2003)

Rapid and Energy-Efficient Testing for Embedded Cores. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (Asian Test Symposium, 2004)

Pair Balance-Based Test Scheduling for SOCs. - Yu Hu 001; Yinhe Han 001; Huawei Li 001; Tao Lv 001; Xiaowei Li 001 (Asian Test Symposium, 2004)

Circuit-Width Based Heuristic for Boolean Reasoning. - Guanghui Li 001; Xiaowei Li 001 (Asian Test Symposium, 2004)

Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test. - Yinhe Han 001; Xiaowei Li 001 (ESA/VLSI, 2004)

Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (DFT, 2004)

A maximum total leakage current estimation method. - Yongjun Xu 001; Zuying Luo; Xiaowei Li 001 (ISCAS (2), 2004)

Conference Reports. - Xiaowei Li 001 (IEEE Des. Test Comput., 2004)

Leakage Current Estimation of CMOS Circuit with Stack Effect. - Yong-Jun Xu 001; Zuying Luo; Xiaowei Li 001; Li-Jian Li; Xianlong Hong (J. Comput. Sci. Technol., 2004)

Design of an efficient memory subsystem for network processor. - Shuguang Gong; Huawei Li 001; Yufeng Xu; Tong Liu; Xiaowei Li 001 (ASP-DAC, 2005)

Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2005)

Vector extraction for average total power estimation. - Yongjun Xu 001; Jinghua Chen; Zuying Luo; Xiaowei Li 001 (ASP-DAC, 2005)

The Automatic Generation of Basis Set of Path for Path Testing. - Guangmei Zhang; Chen Rui; Xiaowei Li 001; Congying Han (Asian Test Symposium, 2005)

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. - Yinhe Han 001; Xiaowei Li 001; Shivakumar Swaminathan; Yu Hu 001; Anshuman Chandra (Asian Test Symposium, 2005)

A State Machine for Detecting C/C++ Memory Faults. - Guangyan Huang; Guangmei Zhang; Xiaowei Li 001; Yunzhan Gong (Asian Test Symposium, 2005)

Non-robust Test Generation for Crosstalk-Induced Delay Faults. - Pei-Fu Shen; Huawei Li 001; Yong-Jun Xu 001; Xiaowei Li 001 (Asian Test Symposium, 2005)

Deterministic and low power BIST based on scan slice overlapping. - Ji Li; Yinhe Han 001; Xiaowei Li 001 (ISCAS (6), 2005)

Validation analysis and test flow optimization of VLSI chip. - Yanzhuo Tan; Yinhe Han 001; Xiaowei Li 001; Feiyin Lu; Yuchuan Chen (ISCAS (6), 2005)

Using MUXs Network to Hide Bunches of Scan Chains. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (ISQED, 2005)

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. - Yu Hu 001; Xiaowei Li 001; Huawei Li 001; Xiaoqing Wen (PRDC, 2005)

Selection of Crosstalk-Induced Faults in Enhanced Delay Test. - Huawei Li 001; Xiaowei Li 001 (J. Electron. Test., 2005)

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. - Yinhe Han 001; Yu Hu 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra; Xiaoqing Wen (IEICE Trans. Inf. Syst., 2005)

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. - Yinhe Han 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra (J. Comput. Sci. Technol., 2005)

Perface. - Xiaowei Li 001 (J. Comput. Sci. Technol., 2005)

Formal Verification Techniques Based on Boolean Satisfiability Problem. - Xiaowei Li 001; Guanghui Li 001; Ming Shao (J. Comput. Sci. Technol., 2005)

An Efficient Evaluation and Vector Generation Method for Observability-Enhanced Statement Coverage. - Wei Lu; Xiu-Tao Yang; Tao Lv 001; Xiaowei Li 001 (J. Comput. Sci. Technol., 2005)

An innovative free memory design for network processors in home network gateway. - Shuguang Gong; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Consumer Electron., 2005)

A Lightweight Scheme for Trust Relationship Establishment in Ubiquitous Sensor Networks. - Lei Xie; Yongjun Xu 001; Xiaowei Li 001; Yuefei Zhu (CIT, 2006)

A Novel Localization Scheme Based on RSS Data for Wireless Sensor Networks. - Hongyang Chen; Ping Deng; Yongjun Xu 001; Xiaowei Li 001 (APWeb Workshops, 2006)

Test data compression based on clustered random access scan. - Yu Hu 001; Cheng Li; Jia Li 022; Yinhe Han 001; Xiaowei Li 001; Wei Wang; Huawei Li 001; Laung-Terng Wang; Xiaoqing Wen (ATS, 2006)

A Scan Chain Adjustment Technology for Test Power Reduction. - Jia Li 022; Yu Hu 001; Xiaowei Li 001 (ATS, 2006)

An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains. - Tao Lv 001; Ling-Yi Liu; Yang Zhao; Huawei Li 001; Xiaowei Li 001 (ATS, 2006)

Fast Packet Classification using Group Bit Vector. - Tong Liu; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (GLOBECOM, 2006)

Clustering Versus Evenly Distributing Energy Dissipation in Wireless Sensor Routing for Prolonging Network Lifetime. - Guangyan Huang; Xiaowei Li 001; Jing He 004 (International Conference on Computational Science (2), 2006)

An on-chip combinational decompressor for reducing test data volume. - Jie Don; Yu Hu 001; Yinhe Han 001; Xiaowei Li 001 (ISCAS, 2006)

Robust Test Generation for Precise Crosstalk-induced Path Delay Faults. - Huawei Li 001; Pei-Fu Shen; Xiaowei Li 001 (VTS, 2006)

Response compaction for system-on-a-chip based on advanced convolutional codes. - Yinhe Han 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (Sci. China Ser. F Inf. Sci., 2006)

Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification. - Tao Lv 001; Jianping Fan 002; Xiaowei Li 001; Ling-Yi Liu (J. Electron. Test., 2006)

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. - Yu Hu 001; Yinhe Han 001; Xiaowei Li 001; Huawei Li 001; Xiaoqing Wen (IEICE Trans. Inf. Syst., 2006)

Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes. - Yinhe Han 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra (IEEE Trans. Instrum. Meas., 2006)

Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic. - Shaohua Lei; Yinhe Han 001; Xiaowei Li 001 (ATS, 2007)

Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects. - Minjin Zhang; Xiaowei Li 001 (ATS, 2007)

A Routing Algorithm for Random Error Tolerance in Network-on-Chip. - Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (HCI (4), 2007)

Bug analysis and corresponding error models in real designs. - Tao Lv 001; Tong Xu; Yang Zhao; Huawei Li 001; Xiaowei Li 001 (HLDVT, 2007)

The design-for-testability features of a general purpose microprocessor. - Da Wang; Xiaoxin Fan; Xiang Fu 007; Hui Liu; Ke Wen; Rui Li; Huawei Li 001; Yu Hu 001; Xiaowei Li 001 (ITC, 2007)

Data Mining via Minimal Spanning Tree Clustering for Prolonging Lifetime of Wireless Sensor Networks. - Guangyan Huang; Xiaowei Li 001; Jing He 004; Xin Li (Int. J. Inf. Technol. Decis. Mak., 2007)

Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment. - Wei Wang; Yu Hu 001; Yinhe Han 001; Xiaowei Li 001; You-Sheng Zhang (J. Comput. Sci. Technol., 2007)

Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. - Yinhe Han 001; Yu Hu 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Robust test generation for power supply noise induced path delay faults. - Xiang Fu 007; Huawei Li 001; Yu Hu 001; Xiaowei Li 001 (ASP-DAC, 2008)

On reducing both shift and capture power for scan-based testing. - Jia Li 022; Qiang Xu 001; Yu Hu 001; Xiaowei Li 001 (ASP-DAC, 2008)

A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. - Fei Wang; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2008)

Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis. - Fei Wang; Yu Hu 001; Yu Huang 005; Jing Ye 001; Xiaowei Li 001 (ATS, 2008)

Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001 (ATS, 2008)

iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. - Jia Li 022; Qiang Xu 001; Yu Hu 001; Xiaowei Li 001 (DATE, 2008)

Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. - Lei Zhang 008; Yinhe Han 001; Qiang Xu 001; Xiaowei Li 001 (DATE, 2008)

Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. - Jia Li 022; Qiang Xu 001; Yu Hu 001; Xiaowei Li 001 (DELTA, 2008)

A Scan-Based Delay Test Method for Reduction of Overtesting. - Hui Liu; Huawei Li 001; Yu Hu 001; Xiaowei Li 001 (DELTA, 2008)

Adaptive Diagnostic Pattern Generation for Scan Chains. - Fei Wang; Yu Hu 001; Xiaowei Li 001 (DELTA, 2008)

A Case Study on At-Speed Testing for a Gigahertz Microprocessor. - Da Wang; Rui Li; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (DELTA, 2008)

Static Crosstalk Noise Analysis with Transition Map. - Minjin Zhang; Huawei Li 001; Xiaowei Li 001 (DELTA, 2008)

On capture power-aware test data compression for scan-based testing. - Jia Li 022; Xiao Liu 011; Yubin Zhang; Yu Hu 001; Xiaowei Li 001; Qiang Xu 001 (ICCAD, 2008)

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects. - Fei Wang; Yu Hu 001; Huawei Li 001; Xiaowei Li 001; Jing Ye 001; Yu Huang 005 (ITC, 2008)

Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains. - Jing Ye 001; Fei Wang; Yu Hu 001; Xiaowei Li 001 (ITC, 2008)

Multiple Coupling Effects Oriented Path Delay Test Generation. - Minjin Zhang; Huawei Li 001; Xiaowei Li 001 (VTS, 2008)

Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001; Yu Hu 001 (VTS, 2008)

BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission. - Guihai Yan; Yinhe Han 001; Xiaowei Li 001; Hui Liu (IEICE Trans. Electron., 2008)

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. - Da Wang; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (J. Comput. Sci. Technol., 2008)

Analysis of Forwarding Mechanisms on Fine-Grain Gradient Sinking Model in WSN. - Limin Sun 001; Hongsong Zhu; Bin Duan; Xiaowei Li 001; Yi Sun 004 (J. Signal Process. Syst., 2008)

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. - Song Jin; Yinhe Han 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001; Guihai Yan (Asian Test Symposium, 2009)

A Low Overhead On-Chip Path Delay Measurement Circuit. - Songwei Pei; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2009)

A unified online Fault Detection scheme via checking of Stability Violation. - Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (DATE, 2009)

MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency. - Guihai Yan; Yinhe Han 001; Hui Liu; Xiaoyao Liang; Xiaowei Li 001 (ISLPED, 2009)

Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy. - Jianbo Dong; Lei Zhang 008; Yinhe Han 001; Guihai Yan; Xiaowei Li 001 (PRDC, 2009)

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. - Binzhang Fu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (PRDC, 2009)

Online Computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures. - Songjun Pan; Yu Hu 001; Xiaowei Li 001 (PRDC, 2009)

Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan. - Songwei Pei; Huawei Li 001; Xiaowei Li 001 (PRDC, 2009)

Impact of Hazards on Pattern Selection for Small Delay Defects. - Jie Wang; Huawei Li 001; Yinghua Min; Xiaowei Li 001; Huaguo Liang (PRDC, 2009)

A New Post-Silicon Debug Approach Based on Suspect Window. - Jianliang Gao; Yinhe Han 001; Xiaowei Li 001 (VTS, 2009)

Automatic Selection of Internal Observation Signals for Design Verification. - Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (VTS, 2009)

A sensor network performance inference algorithm based on passive measurement. - Yu Yang; Yongjun Xu 001; Xiaowei Li 001 (WCNC, 2009)

Preface. - Fei-Yue Wang 001; Ninghui Sun; Wenji Mao; Xiaowei Li 001 (J. Comput. Sci. Technol., 2009)

Selected Crosstalk Avoidance Code for Reliable Network-on-Chip. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001 (J. Comput. Sci. Technol., 2009)

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. - Lei Zhang 008; Yinhe Han 001; Qiang Xu 001; Xiaowei Li 001; Huawei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Graph partition based path selection for testing of small delay defects. - Zijian He; Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2010)

On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing. - Xiang Fu 007; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2010)

An Efficient Algorithm for Finding a Universal Set of Testable Long Paths. - Zijian He; Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2010)

P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework. - Song Jin; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2010)

Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method. - Jing Ye 001; Xiaolin Zhang; Yu Hu 001; Xiaowei Li 001 (Asian Test Symposium, 2010)

Software-Based Self-Testing of Processors Using Expanded Instructions. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2010)

Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. - Binzhang Fu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2010)

An on-chip clock generation scheme for faster-than-at-speed delay testing. - Songwei Pei; Huawei Li 001; Xiaowei Li 001 (DATE, 2010)

Diagnosis of multiple arbitrary faults with mask and reinforcement effect. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (DATE, 2010)

An abstraction-guided simulation approach using Markov models for microprocessor verification. - Tao Zhang; Tao Lv 001; Xiaowei Li 001 (DATE, 2010)

Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors. - Lei Zhang 008; Yue Yu; Jianbo Dong; Yinhe Han 001; Shangping Ren; Xiaowei Li 001 (DATE, 2010)

Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. - Guihai Yan; Xiaoyao Liang; Yinhe Han 001; Xiaowei Li 001 (ISCA, 2010)

On generation of a universal path candidate set containing testable long paths. - Zijian He; Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (ITC, 2010)

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. - Huawei Li 001; Dawen Xu 002; Yinhe Han 001; Kwang-Ting Cheng; Xiaowei Li 001 (ITC, 2010)

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (PRDC, 2010)

Improving complex distributed software system availability through information hiding. - Li Wang 011; Yair Leiferman; Shangping Ren; Kevin A. Kwiat; Xiaowei Li 001 (SAC, 2010)

Fast path selection for testing of small delay defects considering path correlations. - Zijian He; Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (VTS, 2010)

Testable Critical Path Selection Considering Process Variation. - Xiang Fu 007; Huawei Li 001; Xiaowei Li 001 (IEICE Trans. Inf. Syst., 2010)

A Novel Post-Silicon Debug Mechanism Based on Suspect Window. - Jianliang Gao; Yinhe Han 001; Xiaowei Li 001 (IEICE Trans. Inf. Syst., 2010)

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power. - Jun Liu; Yinhe Han 001; Xiaowei Li 001 (IEICE Trans. Inf. Syst., 2010)

Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling. - Jianbo Dong; Lei Zhang 008; Yinhe Han 001; Guihai Yan; Xiaowei Li 001 (J. Syst. Archit., 2010)

X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. - Jia Li 022; Qiang Xu 001; Yu Hu 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Linear Pulse-Coupled Oscillators Model¬ - A New Approach for Time Synchronization in Wireless Sensor Networks. - Zhulin An; Hongsong Zhu; Meilin Zhang; Chaonong Xu; Yongjun Xu 001; Xiaowei Li 001 (Wirel. Sens. Netw., 2010)

Passive Loss Inference in Wireless Sensor Networks Using EM Algorithm. - Yu Yang; Zhulin An; Yongjun Xu 001; Xiaowei Li 001; Canfeng Chen (Wirel. Sens. Netw., 2010)

Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip. - Cheng Liu 008; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2011)

A resilient on-chip router design through data path salvaging. - Cheng Liu 008; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2011)

Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC. - Yuanqing Cheng; Lei Zhang 008; Yinhe Han 001; Jun Liu; Xiaowei Li 001 (Asian Test Symposium, 2011)

A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications. - Yuntan Fang; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2011)

Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs. - Keheng Huang; Yu Hu 001; Xiaowei Li 001; Gengxin Hua; Hongjin Liu; Bo Liu 018 (Asian Test Symposium, 2011)

Wear rate leveling: lifetime enhancement of PRAM with endurance variation. - Jianbo Dong; Lei Zhang 008; Yinhe Han 001; Ying Wang 001; Xiaowei Li 001 (DAC, 2011)

Eliminating data invalidation in debugging multiple-clock chips. - Jianliang Gao; Yinhe Han 001; Xiaowei Li 001 (DATE, 2011)

Cross-layer optimized placement and routing for FPGA soft error mitigation. - Keheng Huang; Yu Hu 001; Xiaowei Li 001 (DATE, 2011)

A cost-effective substantial-impact-filter based method to tolerate voltage emergencies. - Songjun Pan; Yu Hu 001; Xing Hu 001; Xiaowei Li 001 (DATE, 2011)

Flex memory: Exploiting and managing abundant off-chip optical bandwidth. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2011)

On diagnosis of multiple faults using compacted responses. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (DATE, 2011)

Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors. - Shuchang Shan; Yu Hu 001; Xiaowei Li 001 (DSN, 2011)

A greedy approach to tolerate defect cores for multimedia applications. - Ke Yue; Soumia Ghalim; Zheng Li 006; Frank Lockom; Shangping Ren; Lei Zhang 008; Xiaowei Li 001 (ESTIMedia, 2011)

An abacus turn model for time/space-efficient reconfigurable routing. - Binzhang Fu; Yinhe Han 001; Jun Ma; Huawei Li 001; Xiaowei Li 001 (ISCA, 2011)

Online timing variation tolerance for digital integrated circuits. - Guihai Yan; Xiaowei Li 001 (ITC, 2011)

A unified test architecture for on-line and off-line delay fault detections. - Songwei Pei; Huawei Li 001; Xiaowei Li 001 (VTS, 2011)

Scan chain design for shift power reduction in scan-based testing. - Jia Li 022; Yu Hu 001; Xiaowei Li 001 (Sci. China Inf. Sci., 2011)

Oware: Operand width Aware Redundant Execution for Whole-Processor Error Detection. - Yu Hu 001; Zhongliang Chen; Xiaowei Li 001 (Intell. Autom. Soft Comput., 2011)

A Security Mechanism For RFID With Dependable Proxy. - Jun Zhou 022; Yongjun Xu 001; Xiaowei Li 001 (Intell. Autom. Soft Comput., 2011)

A New Multiple-Round Dimension-Order Routing for Networks-on-Chip. - Binzhang Fu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEICE Trans. Inf. Syst., 2011)

Statistical lifetime reliability optimization considering joint effect of process variation and aging. - Song Jin; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (Integr., 2011)

Capture-power-aware test data compression using selective encoding. - Jia Li 022; Xiao Liu 011; Yubin Zhang; Yu Hu 001; Xiaowei Li 001; Qiang Xu 001 (Integr., 2011)

New Methodologies for Parallel Architecture. - Dong-Rui Fan; Xiaowei Li 001; Guo-Jie Li (J. Comput. Sci. Technol., 2011)

ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation. - Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Computers, 2011)

Nonidentical Linear Pulse-Coupled Oscillators Model With Application to Time Synchronization in Wireless Sensor Networks. - Zhulin An; Hongsong Zhu; Xinrong Li; Chaonong Xu; Yongjun Xu 001; Xiaowei Li 001 (IEEE Trans. Ind. Electron., 2011)

A Loss Inference Algorithm for Wireless Sensor Networks to Improve Data Reliability of Digital Ecosystems. - Yu Yang; Yongjun Xu 001; Xiaowei Li 001; Canfeng Chen (IEEE Trans. Ind. Electron., 2011)

MicroFix: Using timing interpolation and delay sensors for power reduction. - Guihai Yan; Yinhe Han 001; Hui Liu; Xiaoyao Liang; Xiaowei Li 001 (ACM Trans. Design Autom. Electr. Syst., 2011)

SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation. - Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Path Delay Test Generation Toward Activation of Worst Case Coupling Effects. - Minjin Zhang; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects. - Ying Zhang 040; Huawei Li 001; Yinghua Min; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Hungarian algorithm based virtualization to maintain application timing similarity for defect-tolerant NoC. - Ke Yue; Frank Lockom; Zheng Li 006; Soumia Ghalim; Shangping Ren; Lei Zhang 008; Xiaowei Li 001 (ASP-DAC, 2012)

SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write. - Yuntan Fang; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2012)

In-Field Testing of NAND Flash Storage: Why and How? - Yu Hu 001; Xinli Gu; Xiaowei Li 001 (Asian Test Symposium, 2012)

A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems. - Jianliang Gao; Jianxin Wang; Yinhe Han 001; Lei Zhang 008; Xiaowei Li 001 (DATE, 2012)

Off-path leakage power aware routing for SRAM-based FPGAs. - Keheng Huang; Yu Hu 001; Xiaowei Li 001; Bo Liu 018; Hongjin Liu; Jian Gong (DATE, 2012)

A lightweight roaming authentication protocol for anonymous wireless communication. - Xiaowei Li 001; Yuqing Zhang 001; Xuefeng Liu 002; Jin Cao 001; Qianqian Zhao (GLOBECOM, 2012)

AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture. - Guihai Yan; Yingmin Li; Yinhe Han 001; Xiaowei Li 001; Minyi Guo; Xiaoyao Liang (HPCA, 2012)

Statistical SDFC: A metric for evaluating test quality of small delay faults. - Xuefeng Zhu; Huawei Li 001; Xiaowei Li 001 (VLSI-DAT, 2012)

Testable Path Selection and Grouping for Faster Than At-Speed Testing. - Xiang Fu 007; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults. - Songjun Pan; Yu Hu 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A High-Precision On-Chip Path Delay Measurement Architecture. - Songwei Pei; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume. - Songwei Pei; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

An energy-efficient link quality monitoring scheme for wireless networks. - Hongsong Zhu; Xinrong Li; Yongjun Xu 001; Xiaowei Li 001; Yan Liu 021 (Wirel. Commun. Mob. Comput., 2012)

Path Constraint Solving Based Test Generation for Hard-to-Reach States. - Yanhong Zhou; Tiancheng Wang; Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2013)

RISO: relaxed network-on-chip isolation for cloud processors. - Hang Lu; Guihai Yan; Yinhe Han 001; Binzhang Fu; Xiaowei Li 001 (DAC, 2013)

Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications. - Xing Hu 001; Guihai Yan; Yu Hu 001; Xiaowei Li 001 (DATE, 2013)

SmartCap: user experience-oriented power adaptation for smartphone's application processor. - Xueliang Li 004; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (DATE, 2013)

Capturing post-silicon variation by layout-aware path-delay testing. - Xiaolin Zhang; Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (DATE, 2013)

HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs. - Enshan Yang; Keheng Huang; Yu Hu 001; Xiaowei Li 001; Jian Gong; Hongjin Liu; Bo Liu 018 (IOLTS, 2013)

Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction. - Yinhe Han 001; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ISCAS, 2013)

On predicting NBTI-induced circuit aging by isolating leakage change. - Yinhe Han 001; Song Jin; Jibing Qiu; Qiang Xu 001; Xiaowei Li 001 (ISQED, 2013)

Tolerating Noise in MLC PCM with Multi-Bit Error Correction Code. - Bing Li 017; Shuchang Shan; Yu Hu 001; Xiaowei Li 001 (PRDC, 2013)

RSAK: Random stream attack for phase change memory in video applications. - Yuntan Fang; Huawei Li 001; Xiaowei Li 001 (VTS, 2013)

A Lightweight Three-Party Privacy-preserving Authentication Key Exchange Protocol Using Smart Card. - Xiaowei Li 001; Yuqing Zhang 001; Xuefeng Liu 002; Jin Cao 001 (KSII Trans. Internet Inf. Syst., 2013)

A New Roaming Authentication Framework For Wireless Communication. - Xiaowei Li 001; Yuqing Zhang 001; Xuefeng Liu 002; Jin Cao 001; Qianqian Zhao (KSII Trans. Internet Inf. Syst., 2013)

TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design. - Yuanqing Cheng; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (J. Comput. Sci. Technol., 2013)

RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router. - Yinhe Han 001; Cheng Liu 008; Hang Lu; Wen-Bo Li; Lei Zhang 008; Xiaowei Li 001 (J. Comput. Sci. Technol., 2013)

A simple and robust anonymous two-factor authenticated key exchange protocol. - Xiaowei Li 001; Yuqing Zhang 001 (Secur. Commun. Networks, 2013)

A new certificateless authenticated key agreement protocol for SIP with different KGCs. - Xiaowei Li 001; Yuqing Zhang 001; Geifei Zhang (Secur. Commun. Networks, 2013)

Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs. - Yuanqing Cheng; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Test Path Selection for Capturing Delay Failures Under Statistical Timing Model. - Zijian He; Tao Lv 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction. - Song Jin; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores. - Jun Ma; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2014)

An On-Line Timing Error Detection Method for Silicon Debug. - Yun Cheng; Huawei Li 001; Xiaowei Li 001 (ATS, 2014)

On-Chip Delay Sensor for Environments with Large Temperature Fluctuations. - Jibing Qiu; Guihai Yan; Xiaowei Li 001 (ATS, 2014)

SuperRange: Wide operational range power delivery design for both STV and NTV computing. - Xin He; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (DATE, 2014)

Partial-SET: Write speedup of PCM main memory. - Bing Li 017; Shuchang Shan; Yu Hu 001; Xiaowei Li 001 (DATE, 2014)

Functional test generation guided by steady-state probabilities of abstract design. - Jian Wang; Huawei Li 001; Tao Lv 001; Tiancheng Wang; Xiaowei Li 001 (DATE, 2014)

Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube. - Yinhe Han 001; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2014)

HARS: A High-Performance Reliable Routing Scheme for 3D NoCs. - Jun Zhou 022; Huawei Li 001; Yuntan Fang; Tiancheng Wang; Yuanqing Cheng; Xiaowei Li 001 (ISVLSI, 2014)

Short-SET: An energy-efficient write scheme for MLC PCM. - Bing Li 017; Yu Hu 001; Xiaowei Li 001 (NVMSA, 2014)

A novel abstraction-guided simulation approach using posterior probabilities for verification. - Jian Wang; Huawei Li 001; Xiaowei Li 001 (VLSI-DAT, 2014)

SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor. - Xueliang Li 004; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (ACM Trans. Design Autom. Electr. Syst., 2014)

Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications. - Yuntan Fang; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels. - Binzhang Fu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications. - Xing Hu 001; Guihai Yan; Yu Hu 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs. - Keheng Huang; Yu Hu 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Test-Quality Optimization for Variable $n$ -Detections of Transition Faults. - Dawen Xu 002; Huawei Li 001; Amirali Ghofrani; Kwang-Ting Cheng; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Diagnose Failures Caused by Multiple Locations at a Time. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001; Wu-Tung Cheng; Yu Huang 005; Huaxing Tang (IEEE Trans. Very Large Scale Integr. Syst., 2014)

ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation. - Hang Lu; Guihai Yan; Yinhe Han 001; Ying Wang 001; Xiaowei Li 001 (ASP-DAC, 2015)

A Lightweight Timing Channel Protection for Shared Memory Controllers. - Guopei Liu; Ying Wang 001; Sen Li; Huawei Li 001; Xiaowei Li 001 (ATS, 2015)

TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs. - Jun Zhou 022; Huawei Li 001; Tiancheng Wang; Sen Li; Ying Wang 001; Xiaowei Li 001 (ATS, 2015)

TURO: A lightweight turn-guided routing scheme for 3D NoCs. - Jun Zhou 022; Huawei Li 001; Tiancheng Wang; Ying Wang 001; Xiaowei Li 001 (COOL Chips, 2015)

Impact assessment of net metering on smart home cyberattack detection. - Yang Liu 064; Shiyan Hu 001; Jie Wu 023; Yiyu Shi 001; Yier Jin; Yu Hu 001; Xiaowei Li 001 (DAC, 2015)

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. - Ying Wang 001; Yinhe Han 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (DAC, 2015)

RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory. - Ying Wang 001; Yinhe Han 001; Cheng Wang; Huawei Li 001; Xiaowei Li 001 (DAC, 2015)

Retraining-based timing error mitigation for hardware neural networks. - Jiachao Deng; Yuntan Fang; Zidong Du; Ying Wang 001; Huawei Li 001; Olivier Temam; Paolo Ienne; David Novo; Xiaowei Li 001; Yunji Chen; Chengyong Wu (DATE, 2015)

OPUF: Obfuscation logic based physical unclonable function. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (IOLTS, 2015)

A case of precision-tunable STT-RAM memory design for approximate neural network. - Ying Wang 001; Lili Song; Yinhe Han 001; Yuanqing Cheng; Huawei Li 001; Xiaowei Li 001 (ISCAS, 2015)

A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans. - Yun Cheng; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ISVLSI, 2015)

A signal degradation reduction method for memristor ratioed logic (MRL) gates. - Bosheng Liu; Ying Wang 001; Zhiqiang You; Yinhe Han 001; Xiaowei Li 001 (IEICE Electron. Express, 2015)

An on-chip frequency programmable test clock generation and application method for small delay defect detection. - Songwei Pei; Huawei Li 001; Song Jin; Jun Liu; Xiaowei Li 001 (Integr., 2015)

A privacy preserving authentication scheme for roaming services in global mobility networks. - Gefei Zhang; Dan Fan; Yuqing Zhang 001; Xiaowei Li 001; Xuefeng Liu 002 (Secur. Commun. Networks, 2015)

RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors. - Hang Lu; Binzhang Fu; Ying Wang 001; Yinhe Han 001; Guihai Yan; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Economizing TSV Resources in 3-D Network-on-Chip Design. - Ying Wang 001; Yinhe Han 001; Lei Zhang 008; Binzhang Fu; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Data Remapping for Static NUCA in Degradable Chip Multiprocessors. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Diagnosis and Layout Aware (DLA) Scan Chain Stitching. - Jing Ye 001; Yu Huang 005; Yu Hu 001; Wu-Tung Cheng; Ruifeng Guo; Liyang Lai; Ting-Pu Tai; Xiaowei Li 001; Wei-pin Changchien; Daw-Ming Lee; Ji-Jan Chen; Sandeep C. Eruvathi; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2015)

ACR: Enabling computation reuse for approximate computing. - Xin He; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2016)

Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm. - Qingli Guo; Jing Ye 001; Yue Gong; Yu Hu 001; Xiaowei Li 001 (ATS, 2016)

Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools. - Yingxin Qiu; Huawei Li 001; Tiancheng Wang; Bo Liu 018; Yingke Gao; Xiaowei Li 001 (ATS, 2016)

POSTER: Attack on Non-Linear Physical Unclonable Function. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (CCS, 2016)

C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization. - Lili Song; Ying Wang 001; Yinhe Han 001; Xin Zhao 044; Bosheng Liu; Xiaowei Li 001 (DAC, 2016)

DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. - Ying Wang 001; Yinhe Han 001; Jun Zhou 022; Huawei Li 001; Xiaowei Li 001 (DAC, 2016)

DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. - Ying Wang 001; Jie Xu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DAC, 2016)

Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage. - Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2016)

DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only). - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (FPGA, 2016)

TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs. - Weina Lu; Yu Hu 001; Jing Ye 001; Xiaowei Li 001 (FPL, 2016)

RPUF: Physical Unclonable Function with Randomized Challenge to resist modeling attack. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (AsianHOST, 2016)

Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices. - Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2016)

An accurate algorithm for computing mutation coverage in model checking. - Huina Chao; Huawei Li 001; Tiancheng Wang; Xiaowei Li 001; Bo Liu 018 (ITC, 2016)

Path constraint solving based test generation for observability-enhanced branch coverage. - Yanhong Zhou; Huawei Li 001; Tiancheng Wang; Bo Liu 018; Yingke Gao; Xiaowei Li 001 (VTS, 2016)

LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs. - Jun Zhou 022; Huawei Li 001; Tiancheng Wang; Xiaowei Li 001 (Integr., 2016)

One-round Secure Key Exchange Protocol With Strong Forward Secrecy. - Xiaowei Li 001; Dengqi Yang; Benhui Chen; Yuqing Zhang 001 (KSII Trans. Internet Inf. Syst., 2016)

Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage Computing. - Xin He; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (J. Comput. Sci. Technol., 2016)

An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores. - Jun Ma; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Computers, 2016)

CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-Level Healthy Condition. - Guihai Yan; Faqiang Sun; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Computers, 2016)

Abstraction-Guided Simulation Using Markov Analysis for Functional Verification. - Jian Wang; Huawei Li 001; Tao Lv 001; Tiancheng Wang; Xiaowei Li 001; Sandip Kundu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving. - Yanhong Zhou; Tiancheng Wang; Huawei Li 001; Tao Lv 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

EcoUp: Towards Economical Datacenter Upgrading. - Guihai Yan; Jun Ma; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Parallel Distributed Syst., 2016)

Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation. - Yinhe Han 001; Jianbo Dong; Kaiheng Weng; Ying Wang 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache. - Ying Wang 001; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. - Ying Wang 001; Yinhe Han 001; Huawei Li 001; Lei Zhang 008; Yuanqing Cheng; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

ApproxEye: Enabling approximate computation reuse for microrobotic computer vision. - Xin He; Guihai Yan; Faqiang Sun; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2017)

BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems. - Shiqi Lian; Ying Wang 001; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2017)

ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory. - Yibin Tang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2017)

CNN-based object detection solutions for embedded heterogeneous multicore SoCs. - Cheng Wang; Ying Wang 001; Yinhe Han 001; Lili Song; Zhenyu Quan; Jiajun Li; Xiaowei Li 001 (ASP-DAC, 2017)

On Evaluating and Constraining Assertions Using Conflicts in Absent Scenarios. - Huina Chao; Huawei Li 001; Xiaoyu Song; Tiancheng Wang; Xiaowei Li 001 (ATS, 2017)

Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems. - Dawen Xu 002; Yi Liao; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (Conf. Computing Frontiers, 2017)

Dadu: Accelerating Inverse Kinematics for High-DOF Robots. - Shiqi Lian; Yinhe Han 001; Ying Wang 001; Yungang Bao; Hang Xiao; Xiaowei Li 001; Ninghui Sun (DAC, 2017)

Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR. - Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (DAC, 2017)

Fault diagnosis of arbiter physical unclonable function. - Jing Ye 001; Qingli Quo; Yu Hu 001; Xiaowei Li 001 (DATE, 2017)

Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators. - Weina Lu; Wenyan Lu; Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (FPL, 2017)

FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks. - Wenyan Lu; Guihai Yan; Jiajun Li; Shijun Gong; Yinhe Han 001; Xiaowei Li 001 (HPCA, 2017)

Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack. - Jing Ye 001; Yue Gong; Yu Hu 001; Xiaowei Li 001 (IOLTS, 2017)

VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (IOLTS, 2017)

GeoCueDepth: Exploiting geometric structure cues to estimate depth from a single image. - Yiming Zeng 003; Yu Hu 001; Shice Liu; Qiankun Tang; Jing Ye 001; Xiaowei Li 001 (IROS, 2017)

Flip-flop clustering based trace signal selection for post-silicon debug. - Yun Cheng; Huawei Li 001; Ying Wang 001; Yingke Gao; Bo Liu 018; Xiaowei Li 001 (VTS, 2017)

Innovative practices session 10C formal verification practices in industry. - Huawei Li 001; Xiaowei Li 001 (VTS, 2017)

LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization. - Yu Hu 001; Jing Ye 001; Zhiping Shi 002; Xiaowei Li 001 (IEICE Trans. Inf. Syst., 2017)

Power-Utility-Driven Write Management for MLC PCM. - Bing Li 017; Yu Hu 001; Ying Wang 001; Jing Ye 001; Xiaowei Li 001 (ACM J. Emerg. Technol. Comput. Syst., 2017)

Retention-Aware DRAM Assembly and Repair for Future FGR Memories. - Ying Wang 001; Yinhe Han 001; Cheng Wang; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Exploiting the Potential of Computation Reuse Through Approximate Computing. - Xin He; Shuhao Jiang; Wenyan Lu; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Multi Scale Comput. Syst., 2017)

PowerTrader: Enforcing Autonomous Power Management for Future Large-Scale Many-Core Processors. - Hang Lu; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Multi Scale Comput. Syst., 2017)

Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs. - Weina Lu; Yu Hu 001; Jing Ye 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. - Lili Song; Ying Wang 001; Yinhe Han 001; Huawei Li 001; Yuanqing Cheng; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips. - Ying Wang 001; Jiachao Deng; Yuntan Fang; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Bias PUF based Secure Scan Chain Design. - Wenjie Li 004; Jing Ye 001; Xiaowei Li 001; Huawei Li 001; Yu Hu 001 (AsianHOST, 2018)

PIMCH: Cooperative memory prefetching in processing-in-memory architecture. - Sheng Xu; Ying Wang 001; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2018)

XORiM: A case of in-memory bit-comparator implementation and its performance implications. - Kaiwei Zou; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2018)

PUF Based Pay-Per-Device Scheme for IP Protection of CNN Model. - Qingli Guo; Jing Ye 001; Yue Gong; Yu Hu 001; Xiaowei Li 001 (ATS, 2018)

RiskCap: Minimizing Effort of Error Regulation for Approximate Computing. - Shuhao Jiang; Jiajun Li; Xin He; Guihai Yan; Xuan Zhang 001; Xiaowei Li 001 (ATS, 2018)

Hardware Trojan in FPGA CNN Accelerator. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (ATS, 2018)

Hardware Trojan Detection Based on Signal Correlation. - Wei Zhao; Haihua Shen; Huawei Li 001; Xiaowei Li 001 (ATS, 2018)

CCR: A concise convolution rule for sparse neural network accelerators. - Jiajun Li; Guihai Yan; Wenyan Lu; Shuhao Jiang; Shijun Gong; Jingya Wu; Xiaowei Li 001 (DATE, 2018)

SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators. - Jiajun Li; Guihai Yan; Wenyan Lu; Shuhao Jiang; Shijun Gong; Jingya Wu; Xiaowei Li 001 (DATE, 2018)

A retrospective evaluation of energy-efficient object detection solutions on embedded devices. - Ying Wang 001; Zhenyu Quan; Jiajun Li; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2018)

Tetris: re-architecting convolutional neural network computation for machine learning accelerators. - Hang Lu; Xin Wei; Ning Lin; Guihai Yan; Xiaowei Li 001 (ICCAD, 2018)

Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors. - Ying Wang 001; Wen Li; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2018)

Grey Zone in Pre-Silicon Hardware Trojan Detection. - Jing Ye 001; Yipei Yang; Yue Gong; Yu Hu 001; Xiaowei Li 001 (ITC-Asia, 2018)

Lightweight Timing Channel Protection for Shared DRAM Controller. - Ying Wang 001; Wen Li; Huawei Li 001; Xiaowei Li 001 (ITC, 2018)

See and Think: Disentangling Semantic Scene Completion. - Shice Liu; Yu Hu 001; Yiming Zeng 003; Qiankun Tang; Beibei Jin; Yinhe Han 001; Xiaowei Li 001 (NeurIPS, 2018)

Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF. - Jing Ye 001; Qingli Guo; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (VTS, 2018)

Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach. - Xiaowei Li 001; Guihai Yan; Jing Ye 001; Ying Wang 001 (Sci. China Inf. Sci., 2018)

Optimizing Memory Efficiency for Deep Convolutional Neural Network Accelerators. - Xiaowei Li 001; Jiajun Li; Guihai Yan (J. Low Power Electron., 2018)

AdaFlow: Aggressive Convolutional Neural Networks Approximation by Leveraging the Input Variability. - Wenyan Lu; Guihai Yan; Xiaowei Li 001 (J. Low Power Electron., 2018)

RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving. - Yiming Zeng 003; Yu Hu 001; Shice Liu; Jing Ye 001; Yinhe Han 001; Xiaowei Li 001; Ninghui Sun (IEEE Robotics Autom. Lett., 2018)

On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug. - Yun Cheng; Huawei Li 001; Ying Wang 001; Haihua Shen; Bo Liu 018; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors. - Ying Wang 001; Huawei Li 001; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators. - Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function. - Jing Ye 001; Qingli Guo; Yu Hu 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection. - Haihua Shen; Huazhe Tan; Huawei Li 001; Feng Zhang 014; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators. - Jiajun Li; Ying Wang 001; Bosheng Liu; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2019)

P3M: a PIM-based neural network model protection scheme for deep learning accelerator. - Wen Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2019)

TNPU: an efficient accelerator architecture for training convolutional neural networks. - Jiajun Li; Guihai Yan; Wenyan Lu; Shuhao Jiang; Shijun Gong; Jingya Wu; Junchao Yan; Xiaowei Li 001 (ASP-DAC, 2019)

Redeeming chip-level power efficiency by collaborative management of the computation and communication. - Ning Lin; Hang Lu; Xin Wei; Xiaowei Li 001 (ASP-DAC, 2019)

Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators. - Bosheng Liu; Xiaoming Chen 003; Ying Wang 001; Yinhe Han 001; Jiajun Li; Haobo Xu; Xiaowei Li 001 (ASP-DAC, 2019)

CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems. - Sheng Xu; Xiaoming Chen 003; Ying Wang 001; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2019)

GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network. - Renjie Lu; Haihua Shen; Yu Su; Huawei Li 001; Xiaowei Li 001 (ATS, 2019)

ShuntFlow: An Efficient and Scalable Dataflow Accelerator Architecture for Streaming Applications. - Shijun Gong; Jiajun Li; Wenyan Lu; Guihai Yan; Xiaowei Li 001 (DAC, 2019)

HeadStart: Enforcing Optimal Inceptions in Pruning Deep Neural Networks for Efficient Inference on GPGPUs. - Ning Lin; Hang Lu; Xin Wei; Xiaowei Li 001 (DAC, 2019)

A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs. - Ying Wang 001; Shengwen Liang; Huawei Li 001; Xiaowei Li 001 (DAC, 2019)

Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Cong Shi 003; Xiaowei Li 001 (DAC, 2019)

Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture. - Kaiwei Zou; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2019)

InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing. - Shengwen Liang; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (FPL, 2019)

MLA: Machine Learning Adaptation for Realtime Streaming Financial Applications. - Jingya Wu; Wenyan Lu; Guihai Yan; Xiaowei Li 001 (IGSC, 2019)

An Agile Precision-Tunable CNN Accelerator based on ReRAM. - Yintao He; Ying Wang 001; Yongchen Wang; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2019)

RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime. - Wen Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCD, 2019)

VNet: A Versatile Network for Efficient Real-Time Semantic Segmentation. - Ning Lin; Hang Lu; Jingliang Gao; Shunjie Qiao; Xiaowei Li 001 (ICCD, 2019)

When Deep Learning Meets the Edge: Auto-Masking Deep Neural Networks for Efficient Machine Learning on Edge Devices. - Ning Lin; Hang Lu; Xing Hu 001; Jingliang Gao; Mingzhe Zhang; Xiaowei Li 001 (ICCD, 2019)

iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack. - Kuozhong Zhang; Junying Huang; Jing Ye 001; Xiaochun Ye; Da Wang; Dongrui Fan; Huawei Li 001; Xiaowei Li 001; Zhimin Zhang 004 (IOLTS, 2019)

Instruction Vulnerability Test and Code Optimization Against DVFS Attack. - Junying Huang; Jing Ye 001; Xiaochun Ye; Da Wang; Dongrui Fan; Huawei Li 001; Xiaowei Li 001; Zhimin Zhang 004 (ITC-Asia, 2019)

Squeezing the Last MHz for CNN Acceleration on FPGAs. - Li Li; Dawen Xu 002; Kouzi Xing; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2019)

Implementation of Parametric Hardware Trojan in FPGA. - Yipei Yang; Jing Ye 001; Xiaowei Li 001; Yinhe Han 001; Huawei Li 001; Yu Hu 001 (ITC-Asia, 2019)

Asian Test Symposium - Past, Present and Future -. - Michiko Inoue; Xiaowei Li 001; Cheng-Wen Wu (ITC, 2019)

China Test Conference (CTC) - Extending the Global Test Forum to China. - Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (ITC, 2019)

Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval. - Shengwen Liang; Ying Wang 001; Youyou Lu; Zhe Yang 012; Huawei Li 001; Xiaowei Li 001 (USENIX ATC, 2019)

Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems. - Wen Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (VTS, 2019)

Scan Chain Based Attacks and Countermeasures: A Survey. - Xiaowei Li 001; Wenjie Li 004; Jing Ye 001; Huawei Li 001; Yu Hu 001 (IEEE Access, 2019)

PIMSim: A Flexible and Detailed Processing-in-Memory Simulator. - Sheng Xu; Xiaoming Chen 003; Ying Wang 001; Yinhe Han 001; Xuehai Qian; Xiaowei Li 001 (IEEE Comput. Archit. Lett., 2019)

Accelerating DNN-based 3D point cloud processing for mobile computing. - Bosheng Liu; Xiaoming Chen 003; Yinhe Han 001; Jiajun Li; Haobo Xu; Xiaowei Li 001 (Sci. China Inf. Sci., 2019)

HTDet: A Clustering Method using Information Entropy for Hardware Trojan Detection. - Renjie Lu; Haihua Shen; Feng Zhang 014; Huawei Li 001; Wei Zhao; Xiaowei Li 001 (CoRR, 2019)

Thread: Towards fine-grained precision reconfiguration in variable-precision neural network accelerator. - Shichang Zhang; Ying Wang 001; Xiaoming Chen 003; Yinhe Han 001; Yujie Wang; Xiaowei Li 001 (IEICE Electron. Express, 2019)

PUFPass: A password management mechanism based on software/hardware codesign. - Qingli Guo; Jing Ye 001; Bing Li 017; Yu Hu 001; Xiaowei Li 001; Yazhu Lan; Guohe Zhang (Integr., 2019)

MV-Net: Toward Real-Time Deep Learning on Mobile GPGPU Systems. - Yibin Tang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ACM J. Emerg. Technol. Comput. Syst., 2019)

SqueezeFlow: A Sparse CNN Accelerator Exploiting Concise Convolution Rules. - Jiajun Li; Shuhao Jiang; Shijun Gong; Jingya Wu; Junchao Yan; Guihai Yan; Xiaowei Li 001 (IEEE Trans. Computers, 2019)

Promoting the Harmony between Sparsity and Regularity: A Relaxed Synchronous Architecture for Convolutional Neural Networks. - Wenyan Lu; Guihai Yan; Jiajun Li; Shijun Gong; Shuhao Jiang; Jingya Wu; Xiaowei Li 001 (IEEE Trans. Computers, 2019)

A QoS-QoR Aware CNN Accelerator Design Approach. - Ying Wang 001; Huawei Li 001; Long Cheng 003; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug. - Yun Cheng; Huawei Li 001; Ying Wang 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors. - Hang Lu; Yisong Chang; Guihai Yan; Ning Lin; Xin Wei; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Comments on "Provably Secure Dynamic Id-Based Anonymous Two-Factor Authenticated Key Exchange Protocol With Extended Security Model". - Xiaowei Li 001; Dengqi Yang; Xing Zeng; Benhui Chen; Yuqing Zhang 001 (IEEE Trans. Inf. Forensics Secur., 2019)

SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks. - Jiajun Li; Guihai Yan; Wenyan Lu; Shijun Gong; Shuhao Jiang; Jingya Wu; Xiaowei Li 001 (ACM Trans. Design Autom. Electr. Syst., 2019)

Search-free Accelerator for Sparse Convolutional Neural Networks. - Bosheng Liu; Xiaoming Chen 003; Yinhe Han 001; Ying Wang 001; Jiajun Li; Haobo Xu; Xiaowei Li 001 (ASP-DAC, 2020)

Survey: Hardware Trojan Detection for Netlist. - Yipei Yang; Jing Ye 001; Yuan Cao 003; Jiliang Zhang 002; Xiaowei Li 001; Huawei Li 001; Yu Hu 001 (ATS, 2020)

Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER. - Yixuan Zhao; Zhiteng Chao; Jing Ye 001; Wen Wang 007; Yuan Cao 003; Shuai Chen; Xiaowei Li 001; Huawei Li 001 (ATS, 2020)

Exploring Spatial-Temporal Multi-Frequency Analysis for High-Fidelity and Temporal-Consistency Video Prediction. - Beibei Jin; Yu Hu 001; Qiankun Tang; Jingyu Niu; Zhiping Shi 002; Yinhe Han 001; Xiaowei Li 001 (CVPR, 2020)

Towards State-Aware Computation in ReRAM Neural Networks. - Yintao He; Ying Wang 001; Xiandong Zhao; Huawei Li 001; Xiaowei Li 001 (DAC, 2020)

An Efficient Deep Learning Accelerator for Compressed Video Analysis. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Yinhe Han 001; Xiaowei Li 001 (DAC, 2020)

Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs. - Qingli Guo; Jing Ye 001; Jiliang Zhang 002; Yu Hu 001; Xiaowei Li 001; Huawei Li 001 (ACM Great Lakes Symposium on VLSI, 2020)

DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators. - Shengwen Liang; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2020)

A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning. - Ying Wang 001; Mengdi Wang; Bing Li 017; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2020)

Two-Stage Safe Reinforcement Learning for High-Speed Autonomous Racing. - Jingyu Niu; Yu Hu 001; Beibei Jin; Yinhe Han 001; Xiaowei Li 001 (SMC, 2020)

Sequence Triggered Hardware Trojan in Neural Network Accelerator. - Zizhen Liu; Jing Ye 001; Xing Hu 001; Huawei Li 001; Xiaowei Li 001; Yu Hu 001 (VTS, 2020)

MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection. - Qingli Guo; Jing Ye 001; Yu Hu 001; Guohe Zhang; Xiaowei Li 001; Huawei Li 001 (IEEE Access, 2020)

Trajectory Tracking Based on Adaptive Sliding Mode Control for Agricultural Tractor. - Chengqiang Yin; Shourui Wang; Xiaowei Li 001; Guanhao Yuan; Chao Jiang (IEEE Access, 2020)

INOR - An Intelligent noise reduction method to defend against adversarial audio examples. - Qingli Guo; Jing Ye 001; Yiran Chen 001; Yu Hu 001; Yazhu Lan; Guohe Zhang; Xiaowei Li 001 (Neurocomputing, 2020)

Evaluating and Constraining Hardware Assertions with Absent Scenarios. - Huina Chao; Huawei Li 001; Xiaoyu Song; Tiancheng Wang; Xiaowei Li 001 (J. Comput. Sci. Technol., 2020)

BZIP: A compact data memory system for UTXO-based blockchains. - Shuhao Jiang; Jiajun Li; Shijun Gong; Junchao Yan; Guihai Yan; Yi Sun 004; Xiaowei Li 001 (J. Syst. Archit., 2020)

Architecting Effectual Computation for Machine Learning Accelerators. - Hang Lu; Mingzhe Zhang; Yinhe Han 001; Qi Wang 025; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

DDSAS: Dynamic and Differentiable Space-Architecture Search. - Longxing Yang; Yu Hu 001; Shun Lu 001; Zihao Sun; Jilin Mei; Yiming Zeng 003; Zhiping Shi 002; Yinhe Han 001; Xiaowei Li 001 (ACML, 2021)

ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption. - Ning Lin; Xiaoming Chen 003; Chunwei Xia; Jing Ye 001; Xiaowei Li 001 (ATS, 2021)

SeGa: A Trojan Detection Method Combined With Gate Semantics. - Yunying Ye; Shan Li; Haihua Shen; Huawei Li 001; Xiaowei Li 001 (ATS, 2021)

DU-DARTS: Decreasing the Uncertainty of Differentiable Architecture Search. - Shun Lu 001; Yu Hu 001; Longxing Yang; Zihao Sun; Jilin Mei; Yiming Zeng 003; Xiaowei Li 001 (BMVC, 2021)

GCiM: A Near-Data Processing Accelerator for Graph Construction. - Lei He 016; Cheng Liu 008; Ying Wang 001; Shengwen Liang; Huawei Li 001; Xiaowei Li 001 (DAC, 2021)

TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning. - Yintao He; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (DAC, 2021)

PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (DAC, 2021)

BitX: Empower Versatile Inference with Hardware Runtime Pruning. - Hongyan Li; Hang Lu; Jiawen Huang; Wenxu Wang; Mingzhe Zhang; Wei Chen; Liang Chang 002; Xiaowei Li 001 (ICPP, 2021)

KFS-LIO: Key-Feature Selection for Lightweight Lidar Inertial Odometry. - Wei Li 235; Yu Hu 001; Yinhe Han 001; Xiaowei Li 001 (ICRA, 2021)

GLIST: Towards In-Storage Graph Learning. - Cangyuan Li; Ying Wang 001; Cheng Liu 008; Shengwen Liang; Huawei Li 001; Xiaowei Li 001 (USENIX ATC, 2021)

Special Session - Test for AI Chips: from DFT to On-line Testing. - Huawei Li 001; Xiaowei Li 001; Yu Huang 005; Ying Wang 001; Gary Guo (VTS, 2021)

Happy Emotion Recognition From Unconstrained Videos Using 3D Hybrid Deep Features. - Najmeh Samadiani; Guangyan Huang; Yu Hu 001; Xiaowei Li 001 (IEEE Access, 2021)

To cloud or not to cloud: an on-line scheduler for dynamic privacy-protection of deep learning workload on edge devices. - Yibin Tang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CCF Trans. High Perform. Comput., 2021)

Internet connected vehicle platoon system modeling and linear stability analysis. - Lidong Zhang; Mengmeng Zhang; Jian Wang; Xiaowei Li 001; Wenxing Zhu (Comput. Commun., 2021)

Energy-Efficient Accelerator Design for Deformable Convolution Networks. - Dawen Xu 002; Cheng Chu; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Kwang-Ting Cheng (CoRR, 2021)

Taming Process Variations in CNFET for Efficient Last Level Cache Design. - Dawen Xu 002; Zhuangyu Feng; Cheng Liu 008; Li Li; Ying Wang 001; Yuanqing Cheng; Huawei Li 001; Xiaowei Li 001 (CoRR, 2021)

Efficient Secure Aggregation Based on SHPRG For Federated Learning. - Zizhen Liu; Si Chen; Jing Ye 001; Junfeng Fan; Huawei Li 001; Xiaowei Li 001 (CoRR, 2021)

ShuntFlowPlus: An Efficient and Scalable Dataflow Accelerator Architecture for Stream Applications. - Shijun Gong; Jiajun Li; Wenyan Lu; Guihai Yan; Xiaowei Li 001 (ACM J. Emerg. Technol. Comput. Syst., 2021)

EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks. - Shengwen Liang; Ying Wang 001; Cheng Liu 008; Lei He 016; Huawei Li 001; Dawen Xu 002; Xiaowei Li 001 (IEEE Trans. Computers, 2021)

Chaotic Weights: A Novel Approach to Protect Intellectual Property of Deep Neural Networks. - Ning Lin; Xiaoming Chen 003; Hang Lu; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

An Edge 3D CNN Accelerator for Low-Power Activity Recognition. - Ying Wang 001; Yongchen Wang; Cong Shi 003; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors. - Dawen Xu 002; Meng He 012; Cheng Liu 008; Ying Wang 001; Long Cheng 003; Huawei Li 001; Xiaowei Li 001; Kwang-Ting Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber. - Jianan Mu; Yixuan Zhao; Zongyue Wang; Jing Ye 001; Junfeng Fan; Shuai Chen; Huawei Li 001; Xiaowei Li 001; Yuan Cao 003 (ASP-DAC, 2022)

InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCs. - Yintao He; Songyun Qu; Ying Wang 001; Bing Li 017; Huawei Li 001; Xiaowei Li 001 (DAC, 2022)

VStore: in-storage graph based vector search accelerator. - Shengwen Liang; Ying Wang 001; Ziming Yuan; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (DAC, 2022)

NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network. - Fuping Li; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (DATE, 2022)

GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. - Fuping Li; Ying Wang 001; Yuanqing Cheng; Yujie Wang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2022)

Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance. - Lei Dai; Ying Wang 001; Cheng Liu 008; Fuping Li; Huawei Li 001; Xiaowei Li 001 (ICCD, 2022)

DOE: Database Offloading Engine for Accelerating SQL Processing. - Wenyan Lu; Yan Chen; Jingya Wu; Yu Zhang 027; Xiaowei Li 001; Guihai Yan (ICDE Workshops, 2022)

AGNAS: Attention-Guided Micro and Macro-Architecture Search. - Zihao Sun; Yu Hu 001; Shun Lu 001; Longxing Yang; Jilin Mei; Yinhe Han 001; Xiaowei Li 001 (ICML, 2022)

Searching for BurgerFormer with Micro-Meso-Macro Space Design. - Longxing Yang; Yu Hu 001; Shun Lu 001; Zihao Sun; Jilin Mei; Yinhe Han 001; Xiaowei Li 001 (ICML, 2022)

Closing the Dynamics Gap via Adversarial and Reinforcement Learning for High-Speed Racing. - Jingyu Niu; Yu Hu 001; Wei Li 235; Guangyan Huang; Yinhe Han 001; Xiaowei Li 001 (IJCNN, 2022)

Exploring the high-throughput and low-delay hardware design of SM4 on FPGA. - Yixiao Chen; Jinfeng Song; Shuai Chen; Yuan Cao 003; Jing Ye 001; Huawei Li 001; Xiaowei Li 001; Xin Lou; Enyi Yao (ISOCC, 2022)

SASH: Efficient secure aggregation based on SHPRG for federated learning. - Zizhen Liu; Si Chen; Jing Ye 001; Junfeng Fan; Huawei Li 001; Xiaowei Li 001 (UAI, 2022)

Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective. - Cheng Liu 008; Zhen Gao 005; Siting Liu 001; Xuefei Ning; Huawei Li 001; Xiaowei Li 001 (VTS, 2022)

Cognitive SSD+: a deep learning engine for energy-efficient unstructured data retrieval. - Shengwen Liang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CCF Trans. High Perform. Comput., 2022)

VNet: a versatile network to train real-time semantic segmentation models on a single GPU. - Wenxing Li; Ning Lin; Mingzhe Zhang; Hang Lu; Xiaoming Chen 003; Xiaowei Li 001 (Sci. China Inf. Sci., 2022)

Fault-Tolerant Deep Learning: A Hierarchical Perspective. - Cheng Liu 008; Zhen Gao 005; Siting Liu 001; Xuefei Ning; Huawei Li 001; Xiaowei Li 001 (CoRR, 2022)

STC-NAS: Fast neural architecture search with source-target consistency. - Zihao Sun; Yu Hu 001; Longxing Yang; Shun Lu 001; Jilin Mei; Yinhe Han 001; Xiaowei Li 001 (Neurocomputing, 2022)

A robust authentication scheme for remote diagnosis and maintenance in 5G V2N. - Ruhui Ma; Jin Cao 001; Dengguo Feng; Hui Li 006; Xiaowei Li 001; Yang Xu (J. Netw. Comput. Appl., 2022)

Portrait: A holistic computation and bandwidth balanced performance evaluation model for heterogeneous systems. - Jingya Wu; Wenyan Lu; Guihai Yan; Xiaowei Li 001 (Sustain. Comput. Informatics Syst., 2022)

CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures. - Kaiwei Zou; Ying Wang 001; Long Cheng 003; Songyun Qu; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Computers, 2022)

Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing. - Yintao He; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning. - Cheng Liu 008; Cheng Chu; Dawen Xu 002; Ying Wang 001; Qianlong Wang; Huawei Li 001; Xiaowei Li 001; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Fast Precision Tuning Solution for Always-On DNN Accelerators. - Ying Wang 001; Yintao He; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Taming Process Variations in CNFET for Efficient Last-Level Cache Design. - Dawen Xu 002; Zhuangyu Feng; Cheng Liu 008; Li Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design - A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach - Xiaowei Li 001; Guihai Yan; Cheng Liu 008 (Springer, 2023)

A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT. - Zhiteng Chao; Senlin Wang; Pengyu Tian; Shuwen Yuan; Huawei Li 001; Jing Ye 001; Xiaowei Li 001 (ATS, 2023)

Adversarial Testing: A Novel On-Line Testing Method for Deep Learning Processors. - Wen Li; Ying Wang 001; Kaiwei Zou; Huawei Li 001; Xiaowei Li 001 (ATS, 2023)

Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design. - Jianan Mu; Huajie Tan; Shuai Chen; Min Cai; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ATS, 2023)

A Template Attack on Reduction Without Reference Device on Kyber. - Yipei Yang; Junying Huang; Zongyue Wang; Jing Ye 001; Zihao Sun; Junfeng Fan; Shuai Chen; Huawei Li 001; Xiaowei Li 001; Yuan Cao 003 (ATS, 2023)

Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array. - Jianan Mu; Huajie Tan; Jiawen Wu; Haotian Lu 002; Chip-Hong Chang; Shuai Chen; Shengwen Liang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2023)

Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants. - Chaofang Ma; Jianan Mu; Jing Ye 001; Shuai Chen; Yuan Cao 003; Huawei Li 001; Xiaowei Li 001 (ETS, 2023)

Co-ViSu: a Video Super-Resolution Accelerator Exploiting Codec Information Reuse. - Haishuang Fan; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (FPL, 2023)

M2VT: A Multi-Output Encoder Accelerator for Multiple-Way Video Transcoding. - Haishuang Fan; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (ACM Great Lakes Symposium on VLSI, 2023)

KPU-SQL: Kernel Processing Unit for High-Performance SQL Acceleration. - Hao Kong; Haishuang Fan; Jingya Wu; Liyun Cheng; Yan Chen; Wenyan Lu; Guihai Yan; Xiaowei Li 001 (ACM Great Lakes Symposium on VLSI, 2023)

Optimize the TX Architecture of RDMA NIC for Performance Isolation in the Cloud Environment. - Yunkun Liao; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (ACM Great Lakes Symposium on VLSI, 2023)

Poseidon: Practical Homomorphic Encryption Accelerator. - Yinghao Yang; Huaizhi Zhang; Shengyu Fan; Hang Lu; Mingzhe Zhang; Xiaowei Li 001 (HPCA, 2023)

DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. - Erjing Luo; Haitong Huang; Cheng Liu 008; Guoyu Li; Bing Yang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2023)

PANG: A Pattern-Aware GCN Accelerator for Universal Graphs. - Yibo Du; Ying Wang 001; Shengwen Liang; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (ICCD, 2023)

BitColor: Accelerating Large-Scale Graph Coloring on FPGA with Parallel Bit-Wise Engines. - Haishuang Fan; Ming Li; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (ICPP, 2023)

Reliability Analysis of Vision Transformers. - Xinghua Xue; Cheng Liu 008; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers. - Xinghua Xue; Cheng Liu 008; Haitong Huang; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

ChipGPT: How far are we from natural language hardware design. - Kaiyan Chang; Ying Wang 001; Haimeng Ren; Mengdi Wang; Shengwen Liang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing. - Haitong Huang; Cheng Liu 008; Xinghua Xue; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

Cross-Layer Optimization for Fault-Tolerant Deep Learning. - Qing Zhang; Cheng Liu 008; Bo Liu 018; Haitong Huang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

Chosen ciphertext correlation power analysis on Kyber. - Yipei Yang; Zongyue Wang; Jing Ye 001; Junfeng Fan; Shuai Chen; Huawei Li 001; Xiaowei Li 001; Yuan Cao 003 (Integr., 2023)

DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning. - Zizhen Liu; Si Chen; Jing Ye 001; Junfeng Fan; Huawei Li 001; Xiaowei Li 001 (J. Supercomput., 2023)

BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks. - Hongyan Li; Hang Lu; Haoxuan Wang; Shengji Deng; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

On-Line Fault Protection for ReRAM-Based Neural Networks. - Wen Li; Ying Wang 001; Cheng Liu 008; Yintao He; Lian Liu; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Computers, 2023)

Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation. - Jianan Mu; Yi Ren; Wen Wang 007; Yizhong Hu; Shuai Chen; Chip-Hong Chang; Junfeng Fan; Jing Ye 001; Yuan Cao 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses. - Cheng Chu; Cheng Liu 008; Dawen Xu 002; Ying Wang 001; Tao Luo 014; Huawei Li 001; Xiaowei Li 001 (ACM Trans. Design Autom. Electr. Syst., 2023)

DOE: database offloading engine for accelerating SQL processing. - Hao Kong; Wenyan Lu; Yan Chen; Jingya Wu; Yu Zhang 027; Guihai Yan; Xiaowei Li 001 (Distributed Parallel Databases, 2023)

Statistical Modeling of Soft Error Influence on Neural Networks. - Haitong Huang; Xinghua Xue; Cheng Liu 008; Ying Wang 001; Tao Luo 014; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance. - Xinghua Xue; Cheng Liu 008; Bo Liu 018; Haitong Huang; Ying Wang 001; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture. - Yinghao Yang; Hang Lu; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Soft Error Reliability Analysis of Vision Transformers. - Xinghua Xue; Cheng Liu 008; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver. - Zhiteng Chao; Xindi Zhang; Junying Huang; Jing Ye 001; Shaowei Cai 001; Huawei Li 001; Xiaowei Li 001 (ASPDAC, 2024)

APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction. - Lei Dai; Shengwen Liang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ASPDAC, 2024)

Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration. - Fuping Li; Ying Wang 001; Yujie Wang; Mengdi Wang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (ASPDAC, 2024)

Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction. - Jiaping Tang; Zizhen Liu; Jianan Mu; Feng Gu; Mingjun Wang; Wenxing Li; Jing Ye 001; Xiaowei Li 001; Huawei Li 001 (ATS, 2024)

TianMen: a DPU-based storage network offloading structure for disaggregated datacenters. - Weiyue Zhao; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (SoCC, 2024)

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. - Kaiyan Chang; Kun Wang 055; Nan Yang; Ying Wang 001; Dantong Jin; Wenlong Zhu; Zhirong Chen; Cangyuan Li; Hao Yan; Yunhao Zhou; Zhuoliang Zhao; Yuan Cheng; et al. (DAC, 2024)

Chiplever: Towards Effortless Extension of Chiplet-based System for FHE. - Yibo Du; Ying Wang 001; Bing Li 017; Fuping Li; Shengwen Liang; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (DAC, 2024)

Co-Via: A Video Frame Interpolation Accelerator Exploiting Codec Information Reuse. - Haishuang Fan; Qichu Sun; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (DAC, 2024)

PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and Energy Efficiency. - Yunkun Liao; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (DAC, 2024)

Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration. - Lian Liu; Zhaohui Xu; Yintao He; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (DAC, 2024)

Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption. - Jianan Mu; Husheng Han; Shangyi Shi; Jing Ye 001; Zizhen Liu; Shengwen Liang; Meng Li 004; Mingzhe Zhang; Song Bian 001; Xing Hu 001; Huawei Li 001; Xiaowei Li 001 (DAC, 2024)

GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction. - Yibo Du; Shengwen Liang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (DATE, 2024)

Bit-Trimmer: Ineffectual Bit-Operation Removal for CLM Architecture. - Yintao He; Shixin Zhao; Songyun Qu; Huawei Li 001; Xiaowei Li 001; Ying Wang 001 (DATE, 2024)

HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System. - Shengwen Liang; Ziming Yuan; Ying Wang 001; Dawen Xu 002; Huawei Li 001; Xiaowei Li 001 (DATE, 2024)

A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256. - Han Yan; Shuai Chen; Junying Huang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ETS, 2024)

Athena: Add More Intelligence to RMT-Based Network Data Plane with Low-Bit Quantization. - Yunkun Liao; Hanyue Lin; Jingya Wu; Wenyan Lu; Huawei Li 001; Xiaowei Li 001; Guihai Yan (Euro-Par (2), 2024)

Efficient RNIC Cache Side-Channel Attack Detection Through DPU-Driven Architecture. - Yunkun Liao; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (Euro-Par (2), 2024)

AGC: A Unified Architecture for Accelerating K-Nearest Neighbor Graph Construction in Vector Search. - Lei Dai; Ziming Yuan; Wen Li; Shengwen Liang; Kaiwei Zou; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2024)

DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism. - Feng Gu; Mingjun Wang; Jianan Mu; Zizhen Liu; Jiaping Tang; Hui Wang 152; Yonghao Wang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2024)

HLSPilot: LLM-based High-Level Synthesis. - Chenwei Xiong; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2024)

AMST: Accelerating Large-Scale Graph Minimum Spanning Tree Computation on FPGA. - Haishuang Fan; Rui Meng; Qichu Sun; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (IPDPS, 2024)

A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification. - Zhiteng Chao; Qinluan Dai; Jiale Li; Zizhen Liu; Wenxing Li; Hongqin Lyu; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2024)

Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262. - Mingjun Wang; Hui Wang 152; Jianan Mu; Zizhen Liu; Jun Gao; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2024)

ApproxPilot: A GNN-based Accelerator Approximation Framework. - Qing Zhang; Cheng Liu 008; Siting Liu 001; Yajuan Hui; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

SigDLA: A Deep Learning Accelerator Extension for Signal Processing. - Fangfa Fu; Wenyu Zhang; Zesong Jiang; Zhiyu Zhu; Guoyu Li; Bing Yang; Cheng Liu 008; Liyi Xiao; Jinxiang Wang 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation. - Xinmiao Zhang 004; Zheng Feng; Shengwen Liang; Xinyu Chen 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA. - Zesong Jiang; Qing Zhang; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

MCU-MixQ: A HW/SW Co-optimized Mixed-precision Neural Network Design Framework for MCUs. - Junfeng Gong; Cheng Liu 008; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

COMET: Towards Partical W4A4KV4 LLMs Serving. - Lian Liu; Haimeng Ren; Long Cheng 003; Zhaohui Xu; Yudong Pan; Mengdi Wang; Xiaowei Li 001; Yinhe Han 001; Ying Wang 001 (CoRR, 2024)

DRIM-ANN: An Approximate Nearest Neighbor Search Engine based on Commercial DRAM-PIMs. - Mingkai Chen; Tianhua Han; Cheng Liu 008; Shengwen Liang; Kuai Yu; Lei Dai; Ziming Yuan; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

SPFL: A Self-Purified Federated Learning Method Against Poisoning Attacks. - Zizhen Liu; Weiyang He; Chip-Hong Chang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Inf. Forensics Secur., 2024)

Mortar-FP8: Morphing the Existing FP32 Infrastructure for High-Performance Deep Learning Acceleration. - Hongyan Li; Hang Lu; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

PDG: A Prefetcher for Dynamic Graph Updating. - Xinmiao Zhang 004; Cheng Liu 008; Jiacheng Ni; Yuanqing Cheng; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

General Purpose Deep Learning Accelerator Based on Bit Interleaving. - Liang Chang 002; Hang Lu; Chenglong Li; Xin Zhao 044; Zhicheng Hu; Jun Zhou 017; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Automatic Neural Network Architecture-and-Quantization Joint Optimization Framework for Efficient Model Inference. - Lian Liu; Ying Wang 001; Xiandong Zhao; Weiwei Chen; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating. - Mingkai Chen; Cheng Liu 008; Shengwen Liang; Lei He 016; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing. - Haitong Huang; Cheng Liu 008; Xinghua Xue; Bo Liu 018; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

DPU-Direct: Unleashing Remote Accelerators via Enhanced RDMA for Disaggregated Datacenters. - Yunkun Liao; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (IEEE Trans. Computers, 2024)

A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks. - Yintao He; Bing Li 017; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Dep-TEE: Decoupled Memory Protection for Secure and Scalable Inter-enclave Communication on RISC-V. - Shangjie Pan; Xuanyao Peng; Zeyuan Man; Xiquan Zhao; Dongrong Zhang; Bicheng Yang; Dong Du 003; Hang Lu; Yubin Xia; Xiaowei Li 001 (ASP-DAC, 2025)

APTO: Accelerating Serialization-Based Point Cloud Transformers with Position-Aware Pruning. - Qichu Sun; Rui Meng; Haishuang Fan; Fangqiang Ding; Linxi Lu; Jingya Wu; Xiaowei Li 001; Guihai Yan (ASP-DAC, 2025)

ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring. - Mingjun Wang; Hui Wang 152; Zizhen Liu; Feng Gu; Jianan Mu; Jiaping Tang; Jun Gao; Huawei Li 001; Jing Ye 001; Xiaowei Li 001 (ASP-DAC, 2025)

PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System. - Yintao He; Haiyu Mao; Christina Giannoula; Mohammad Sadrosadati; Juan Gómez-Luna; Huawei Li 001; Xiaowei Li 001; Ying Wang 001; Onur Mutlu (ASPLOS (2), 2025)

COMET: Towards Practical W4A4KV4 LLMs Serving. - Lian Liu; Long Cheng 003; Haimeng Ren; Zhaohui Xu; Yudong Pan; Mengdi Wang; Xiaowei Li 001; Yinhe Han 001; Ying Wang 001 (ASPLOS (2), 2025)

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. - Jiaping Tang; Jianan Mu; Silin Liu; Zizhen Liu; Feng Gu; Xinyu Zhang; Leyan Wang; Shengwen Liang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2025)

Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM. - Lian Liu; Shixin Zhao; Bing Li 017; Haimeng Ren; Zhaohui Xu; Mengdi Wang; Xiaowei Li 001; Yinhe Han 001; Ying Wang 001 (HPCA, 2025)

Hydra: Scale-out FHE Accelerator Architecture for Secure Deep Learning on FPGA. - Yinghao Yang; Xicheng Xu; Haibin Zhang; Jie Song; Xin Tang; Hang Lu; Xiaowei Li 001 (HPCA, 2025)

NeuVSA: A Unified and Efficient Accelerator for Neural Vector Search. - Ziming Yuan; Lei Dai; Wen Li; Jie Zhang 048; Shengwen Liang; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001; Jiafeng Guo; Peng Wang 037; Renhai Chen; et al. (HPCA, 2025)

FrontOrder: Frontier-Guided Graph Reordering. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Chenwei Xiong; Yu Zhang 027; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (ICDE, 2025)

Taijigraph: an Out-Of-Core Graph Processing System Enhanced with Computational Storage. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Hayden Kwok-Hay So; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IPDPS, 2025)

Frontier-guided Graph Reordering. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Chenwei Xiong; Yu Zhang 027; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (PPoPP, 2025)

HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion. - Zhiteng Chao; Bin Sun; Hongqin Lyu; Ge Yu; Minjun Wang; Wenxing Li; Zizhen Liu; Jianan Mu; Shengwen Liang; Jing Ye 001; Xiaowei Li 001; Huawei Li 001 (VTS, 2025)

A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow. - Zhiteng Chao; Xindi Zhang; Junying Huang; Zizhen Liu; Yixuan Zhao; Jing Ye 001; Shaowei Cai 001; Huawei Li 001; Xiaowei Li 001 (Integr., 2025)

APoX-M: Accelerate deep point cloud analysis via adaptive graph construction. - Lei Dai; Shengwen Liang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (Integr., 2025)

Sharing Can be Threatening: Uncovering Security Flaws of RBAC Model on Smart Home Platforms. - Yiyu Yang; Jiayu Zhao; Yilian Li; Xiaowei Li 001; Peng Liu 005; Yuqing Zhang 001 (IEEE Trans. Dependable Secur. Comput., 2025)

FlexMem: High-Parallel Near-Memory Architecture for Flexible Dataflow in Fully Homomorphic Encryption. - Shangyi Shi; Husheng Han; Jianan Mu; Xinyao Zheng; Ling Liang; Hang Lu; Zidong Du; Xiaowei Li 001; Xing Hu 001; Qi Guo 001 (CoRR, 2025)

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. - Jiaping Tang; Jianan Mu; Silin Liu; Zizhen Liu; Feng Gu; Xinyu Zhang; Leyan Wang; Shenwen Liang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2025)

Trident: The Acceleration Architecture for High-Performance Private Set Intersection. - Jinkai Zhang; Yinghao Yang; Zhe Zhou; Zhicheng Hu; Xin Zhao 044; Liang Chang 002; Hang Lu; Xiaowei Li 001 (IEEE Trans. Computers, 2025)

FUS: FPGA-based Universal Sketch with homogeneous and heterogeneous memory architectures. - Yunkun Liao; Jingya Wu; Wenyan Lu; Huawei Li 001; Xiaowei Li 001; Guihai Yan (CCF Trans. High Perform. Comput., 2025)

FicGCN: Unveiling the Homomorphic Encryption Efficiency from Irregular Graph Convolutional Networks. - Zhaoxuan Kan; Husheng Han; Shangyi Shi; Tenghui Hua; Hang Lu; Xiaowei Li 001; Jianan Mu; Xing Hu 001 (CoRR, 2025)

Functional Testing and Repair for ReRAM-Based Deep-Learning Accelerators. - Wen Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Kaiwei Zou (IEEE Des. Test, 2025)

TL-PBFT: An Improved PBFT Consensus Algorithm Based on Tree-layered Communication Structure. - Liliang Lei; Guifeng Wu; Dengqi Yang; Benhui Chen; Xiaowei Li 001 (KSII Trans. Internet Inf. Syst., 2025)

KPU: Kernel Processing Unit for in-Memory Analytical Query Processing. - Jingya Wu; Wenyan Lu; Haishuang Fan; Hao Kong; Xiaowei Li 001; Guihai Yan (IEEE Trans. Computers, 2025)

DNA: A General Dynamic Neural Network Accelerator. - Lian Liu; Jinxin Yu; Mengdi Wang; Xiaowei Li 001; Yinhe Han 001; Ying Wang 001 (IEEE Trans. Computers, 2025)

Co-ViSu: Accelerating Video Super-Resolution With Codec Information Reuse. - Haishuang Fan; Qichu Sun; Jingya Wu; Wenyan Lu; Xiaowei Li 001; Guihai Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)