STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures. - Xiaoxiao Liu 001; Yong Li 009; Yaojun Zhang; Alex K. Jones; Yiran Chen 001 (ASP-DAC, 2014)

A heterogeneous computing system with memristor-based neuromorphic accelerators. - Xiaoxiao Liu 001; Mengjie Mao; Hai Li 001; Yiran Chen 001; Hao Jiang 014; J. Joshua Yang; Qing Wu 002; Mark Barnell (HPEC, 2014)

Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper). - Hai Li 001; Xiaoxiao Liu 001; Mengjie Mao; Yiran Chen 001; Qing Wu 002; Mark Barnell (ISIC, 2014)

Emerging memristor technology enabled next generation cortical processor. - Hai Li 001; Miao Hu 002; Xiaoxiao Liu 001; Mengjie Mao; Chuandong Li 001; Shukai Duan 001 (SoCC, 2014)

An efficient STT-RAM-based register file in GPU architectures. - Xiaoxiao Liu 001; Mengjie Mao; Xiuyuan Bi; Hai Li 001; Yiran Chen 001 (ASP-DAC, 2015)

RENO: a high-efficient reconfigurable neuromorphic computing accelerator design. - Xiaoxiao Liu 001; Mengjie Mao; Beiye Liu; Hai Li 001; Yiran Chen 001; Boxun Li; Yu Wang 002; Hao Jiang 014; Mark Barnell; Qing Wu 002; Jianhua Joshua Yang (DAC, 2015)

The applications of memristor devices in next-generation cortical processor designs. - Hai Li 001; Beiye Liu; Xiaoxiao Liu 001; Mengjie Mao; Yiran Chen 001; Qing Wu 002; Qinru Qiu (ISCAS, 2015)

Hardware acceleration for neuromorphic computing: An evolving view. - Beiye Liu; Xiaoxiao Liu 001; Chenchen Liu; Wei Wen; M. Meng; Hai Li 001; Yiran Chen 001 (NVMTS, 2015)

TEMP: thread batch enabled memory partitioning for GPU. - Mengjie Mao; Wujie Wen; Xiaoxiao Liu 001; Jingtong Hu; Danghui Wang; Yiran Chen 001; Hai Li 001 (DAC, 2016)

Heterogeneous systems with reconfigurable neuromorphic computing accelerators. - Sicheng Li 001; Xiaoxiao Liu 001; Mengjie Mao; Hai (Helen) Li; Yiran Chen 001; Boxun Li; Yu Wang 002 (ISCAS, 2016)

Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators. - Xiaoxiao Liu 001; Mengjie Mao; Beiye Liu; Boxun Li; Yu Wang 002; Hao Jiang 014; Mark Barnell; Qing Wu 002; Jianhua Joshua Yang; Hai Li 001; Yiran Chen 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems. - Xiaoxiao Liu 001; Wei Wen; Xuehai Qian; Hai Li 001; Yiran Chen 001 (ASP-DAC, 2018)

Neuromorphic computing's yesterday, today, and tomorrow - an evolutional view. - Yiran Chen 001; Hai (Helen) Li; Chunpeng Wu; Chang Song 001; Sicheng Li 001; Chuhan Min; Hsin-Pai Cheng; Wei Wen; Xiaoxiao Liu 001 (Integr., 2018)

Thread Batching for High-performance Energy-efficient GPU Memory Design. - Bing Li 017; Mengjie Mao; Xiaoxiao Liu 001; Tao Liu 023; Zihao Liu; Wujie Wen; Yiran Chen 001; Hai (Helen) Li (ACM J. Emerg. Technol. Comput. Syst., 2019)

Exploring Applications of STT-RAM in GPU Architectures. - Xiaoxiao Liu 001; Mengjie Mao; Xiuyuan Bi; Hai Helen Li; Yiran Chen 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Ecco: Improving Memory Bandwidth and Capacity for LLMs via Entropy-Aware Cache Compression. - Feng Cheng; Cong Guo 003; Chiyue Wei; Junyao Zhang; Changchun Zhou 001; Edward Hanson; Jiaqi Zhang 002; Xiaoxiao Liu 001; Hai Li 001; Yiran Chen 001 (ISCA, 2025)