Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm. - Xiaoxin Cui; Dunshan Yu; Shimin Sheng; Xiaole Cui (APCCAS, 2006)

A JTAG-based configuration circuit applied in SerDes chip. - Xun Jiang; Xiaoxin Cui; Dunshan Yu (ASICON, 2011)

AHardware implementation of DES with combined countermeasure against DPA. - Xiaoxin Cui; Rui Li; Wei Wei; Juan Gu; Xiaole Cui (ASICON, 2013)

New DfT architectures for 3D-SICs with a wireless test port. - Yibo He; Xiaole Cui; Chung Len Lee 001; Xiaoxin Cui; Yufeng Jin (ASICON, 2013)

A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs. - Xiaoxin Cui; Kaisheng Ma; Kai Liao; Nan Liao; Di Wu; Wei Wei; Rui Li; Dunshan Yu (ISCAS, 2013)

Leakage Power Reduction of Adiabatic Circuits Based on FinFET Devices. - Kai Liao; Xiaoxin Cui; Nan Liao; Kaisheng Ma (IEICE Trans. Electron., 2013)

High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2m). - Kai Liao; Xiaoxin Cui; Nan Liao; Tian Wang; Xiao Zhang; Ying Huang; Dunshan Yu (ISCAS, 2014)

Low power adiabatic logic based on FinFETs. - Nan Liao; Xiaoxin Cui; Kai Liao; Kaisheng Ma; Di Wu; Wei Wei; Rui Li; Dunshan Yu (Sci. China Inf. Sci., 2014)

Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs. - Kai Liao; Xiaoxin Cui; Nan Liao; Kaisheng Ma; Di Wu; Wei Wei; Rui Li; Dunshan Yu (Sci. China Inf. Sci., 2014)

A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications. - Nan Liao; Xiaoxin Cui; Tian Wang; Kai Liao; Yewen Ni; Dunshan Yu; Xiaole Cui (ASICON, 2015)

A countermeasure for power analysis to scalar multiplication of ECC hardware. - Lifei Liu; Xiaole Cui; Yalin Ran; Xiaoxin Cui (ASICON, 2015)

Employing the mixed FBB/RBB in the design of FinFET logic gates. - Tian Wang; Xiaoxin Cui; Kai Liao; Nan Liao; Yewen Ni; Dunshan Yu; Xiaole Cui (ASICON, 2015)

Key characterization factors of accurate power modeling for FinFET circuits. - Kaisheng Ma; Xiaoxin Cui; Kai Liao; Nan Liao; Di Wu; Dunshan Yu (Sci. China Inf. Sci., 2015)

Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure. - Zuolin Cheng; Xiaole Cui; Xiaoxin Cui; Chung Len Lee 001 (IET Comput. Digit. Tech., 2015)

Ultralow-power high-speed flip-flop based on multimode FinFETs. - Kai Liao; Xiaoxin Cui; Nan Liao; Tian Wang; Dunshan Yu; Xiaole Cui (Sci. China Inf. Sci., 2016)

Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology. - Tian Wang; Xiaoxin Cui; Kai Liao; Nan Liao; Xiaole Cui; Dunshan Yu (IEICE Trans. Electron., 2016)

A practical cold boot attack on RSA private keys. - Tian Wang; Xiaoxin Cui; Yewen Ni; Dunshan Yu; Xiaole Cui; Gang Qu 001 (AsianHOST, 2017)

A hybrid fault model for differential fault attack on AES. - Yixia Liu; Xiaoxin Cui; Jian Cao 002; Xing Zhang 002 (ASICON, 2017)

Design of router for spiking neural networks. - Yewen Ni; Xiaoxin Cui; Yuanning Fan; Qiankun Han; Kefei Liu 002; Xiaole Cui (ASICON, 2017)

Improving DFA on AES using all-fault ciphertexts. - Yewen Ni; Xiaoxin Cui; Tian Wang; Yuanning Fan; Qiankun Han; Kefei Liu 002; Xiaole Cui (ASICON, 2017)

A design of high performance full adder with memristors. - Kuimin Zhang; Xiaole Cui; Xiaoxin Cui (ASICON, 2017)

A signal noise separation method for the instant mixing linear and nonlinear circuits with MISEP algorithm. - Liwen Zhu 002; Xiaole Cui; Xiang Li; Xiaoxin Cui (ASICON, 2017)

A Heuristic Algorithm for Automatic Generation of March Tests. - Xiaole Cui; Yichi Luo; Qiujun Lin; Xiaoxin Cui (ATS, 2017)

Testing of 1TnR RRAM array with sneak path technique. - Xiaole Cui; Qiang Zhang; Xiaoxin Cui; Xin'an Wang; Jinfeng Kang; Xiaoyan Liu (Sci. China Inf. Sci., 2017)

Improving DFA attacks on AES with unknown and random faults. - Nan Liao; Xiaoxin Cui; Kai Liao; Tian Wang; Dunshan Yu; Xiaole Cui (Sci. China Inf. Sci., 2017)

High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ). - Kai Liao; Xiaoxin Cui; Nan Liao; Tian Wang; Dunshan Yu; Xiaole Cui (IEEE Trans. Ind. Electron., 2017)

An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias. - Xiaole Cui; Xiaoxin Cui; Yewen Ni; Min Miao; Yufeng Jin (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Polymorphic gate based IC watermarking techniques. - Tian Wang; Xiaoxin Cui; Dunshan Yu; Omid Aramoon; Timothy Dunlap; Gang Qu 001; Xiaole Cui (ASP-DAC, 2018)

A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition. - Cheng Li; Yuan Wang 001; Jin Zhang; Xiaoxin Cui; Ru Huang 001 (BioCAS, 2018)

A Novel Polymorphic Gate Based Circuit Fingerprinting Technique. - Tian Wang; Xiaoxin Cui; Dunshan Yu; Omid Aramoon; Timothy Dunlap; Gang Qu 001; Xiaole Cui (ACM Great Lakes Symposium on VLSI, 2018)

Design of Low-Power High-Performance FinFET Standard Cells. - Tian Wang; Xiaoxin Cui; Kai Liao; Nan Liao; Dunshan Yu; Xiaole Cui (Circuits Syst. Signal Process., 2018)

Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits. - Tian Wang; Xiaoxin Cui; Yewen Ni; Dunshan Yu; Xiaole Cui (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing. - Yi-Hsiang Chen; Xiaoxin Cui; Kanglin Xiao; Dunshan Yu (ASICON, 2019)

BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware Overhead. - Jiexian Ge; Xiaoxin Cui; Kanglin Xiao; Chenglong Zou; Yi-Hsiang Chen; Rongshan Wei (ASICON, 2019)

Deep Spiking Convolutional Neural Networks for Programmable Neuro-synaptic System. - Chenglong Zou; Xin'an Wang; Boxing Xu; Yisong Kuang; Xiaoxin Cui (ASICON, 2019)

An Energy-Efficient Computing-in-Memory Neuromorphic System with On-Chip Training. - Zhao Zhao; Yuan Wang 001; Xinyue Zhang 002; Xiaoxin Cui; Ru Huang 001 (BioCAS, 2019)

A Sparse Event-Driven Unsupervised Learning Network with Adaptive Exponential Integrate-and-Fire Model. - Zhao Zhao; Yuan Wang 001; Cheng Li; Xiaoxin Cui; Ru Huang 001 (ICICDT, 2019)

A Testability Enhancement Method for the Memristor Ratioed Logic Circuits. - Li Qu; Xiaole Cui; Xiaoxin Cui (ATS, 2020)

A Novel Conversion Method for Spiking Neural Network using Median Quantization. - Chenglong Zou; Xiaoxin Cui; Jiexian Ge; Hanghang Ma; Xin'an Wang (ISCAS, 2020)

A synthesis method for logic circuits in RRAM arrays. - Xiaole Cui; Xiao Ma; Feng Wei; Xiaoxin Cui (Sci. China Inf. Sci., 2020)

Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates. - Xiaole Cui; Xiao Ma; Qiujun Lin; Xiang Li; Hang Zhou; Xiaoxin Cui (Circuits Syst. Signal Process., 2020)

The synthesis method of logic circuits based on the iMemComp gates. - Xiaole Cui; Qiujun Lin; Xiaoxin Cui; Feng Wei; Xiaoyan Liu; Jinfeng Kang (Integr., 2020)

A Novel Circuit Authentication Scheme Based on Partial Polymorphic Gates. - Timothy Dunlap; Omid Aramoon; Gang Qu 001; Tian Wang; Xiaoxin Cui; Dunshan Yu (AsianHOST, 2021)

The logic obfuscation of LFSR with the crosstalk based polymorphic gate. - Yuqian Sun; Xiaole Cui; Yongliang Chen; Xiaoxin Cui (AsianHOST, 2021)

A fully asynchronous QDI mesh router based on 28nm standard cells. - Qingyun Zou; Xiaoxin Cui; Yi Zhong; Zhenhui Dai; Yisong Kuang (ASICON, 2021)

The Modeling Attack and Security Enhancement of the XbarPUF with Both Column Swapping and XORing. - Yongliang Chen; Xiaole Cui; Wenqiang Ye; Xiaoxin Cui (ACM Great Lakes Symposium on VLSI, 2021)

An SNN-Based and Neuromorphic-Hardware-Implementable Noise Filter with Self-adaptive Time Window for Event-Based Vision Sensor. - Kanglin Xiao; Xiaoxin Cui; Kefei Liu 002; Xiaole Cui; Xin'an Wang (IJCNN, 2021)

A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. - Yisong Kuang; Xiaoxin Cui; Yi Zhong; Kefei Liu 002; Chenglong Zou; Zhenhui Dai; Dunshan Yu; Yuan Wang 001; Ru Huang 001 (ISCAS, 2021)

A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS. - Yi Zhong; Xiaoxin Cui; Yisong Kuang; Kefei Liu 002; Yuan Wang 001; Ru Huang 001 (ISCAS, 2021)

The ANN Based Modeling Attack and Security Enhancement of the Double-layer PUF. - Xiaole Cui; Yongliang Chen; Wenqiang Ye; Xiaoxin Cui (ITC-Asia, 2021)

The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack. - Yongliang Chen; Xiaole Cui; Wenqiang Ye; Xiaoxin Cui (ITC, 2021)

The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates. - Xiaole Cui; Ye Ma; Feng Wei; Xiaoxin Cui (IEEE Access, 2021)

Integer-Only Neural Network Quantization Scheme Based on Shift-Batch-Normalization. - Qingyu Guo; Yuan Wang 001; Xiaoxin Cui (CoRR, 2021)

28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance. - Qingyun Zou; Xiaoxin Cui; Zhenhui Dai; Yisong Kuang; Yi Zhong; Chenglong Zou; Xiaole Cui (IEICE Electron. Express, 2021)

Machine Learning Aided Key-Guessing Attack Paradigm Against Logic Block Encryption. - Yi Zhong; Jianhua Feng; Xiaoxin Cui; Xiaole Cui (J. Comput. Sci. Technol., 2021)

A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS. - Yisong Kuang; Xiaoxin Cui; Yi Zhong; Kefei Liu 002; Chenglong Zou; Zhenhui Dai; Yuan Wang 001; Dunshan Yu; Ru Huang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Mapping Model of SNNs to Neuromorphic Hardware. - Xiuping Cui; Xiaochen Hao; Yun Liang 001; Guangyu Sun 003; Xiaoxin Cui; Yuan Wang 001; Ru Huang 001 (AICAS, 2022)

A Full-Neuron Memory Model Designed for Neuromorphic Systems. - Kefei Liu 002; Xiaoxin Cui; Chenglong Zou; Yisong Kuang; Yi Zhong; Kanglin Xiao; Yuan Wang 001 (AICAS, 2022)

A Hybrid Spiking Recurrent Neural Network on Hardware for Efficient Emotion Recognition. - Chenglong Zou; Xiaoxin Cui; Yisong Kuang; Yuan Wang 001; Xinan Wang (AICAS, 2022)

An obfuscation scheme of scan chain to protect the cryptographic chips. - Huixian Huang; Xiaole Cui; Shuming Zhang; Ge Li; Xiaoxin Cui (ATS, 2022)

A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Xin'an Wang; Yuan Wang 001 (ICTA, 2022)

An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells. - Xiaole Cui; Fan Liu; Sunrui Zhang; Xiaoxin Cui (ISCAS, 2022)

A 4-bit Integer-Only Neural Network Quantization Method Based on Shift Batch Normalization. - Qingyu Guo; Xiaoxin Cui; Jian Zhang; Aifei Zhang; Xinjie Guo; Yuan Wang 001 (ISCAS, 2022)

An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight. - Yisong Kuang; Xiaoxin Cui; Chenglong Zou; Yi Zhong; Zhenhui Dai; Zilin Wang; Kefei Liu 002; Dunshan Yu; Yuan Wang 001 (ISCAS, 2022)

A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro. - Nanbing Pan; Xiaoxin Cui; Xin Qiao; Kanglin Xiao; Qingyu Guo; Yuan Wang 001 (ISCAS, 2022)

A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Nanbing Pan; Xin'an Wang; Yuan Wang 001 (ISCAS, 2022)

A Comparative Study on the Performance and Security Evaluation of Spiking Neural Networks. - Yanjie Li; Xiaoxin Cui; Yihao Zhou; Ying Li 056 (IEEE Access, 2022)

Towards Lossless ANN-SNN Conversion under Ultra-Low Latency with Dual-Phase Optimization. - Ziming Wang; Shuang Lian; Yuhao Zhang 007; Xiaoxin Cui; Rui Yan 005; Huajin Tang (CoRR, 2022)

A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec. - Chen Wei; Xiaole Cui; Xiaoxin Cui (IEEE Des. Test, 2022)

A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Xin'an Wang; Yuan Wang 001 (Microelectron. J., 2022)

Modular building blocks for mapping spiking neural networks onto a programmable neuromorphic processor. - Chenglong Zou; Xiaoxin Cui; Guang Chen; Shuo Feng; Kefei Liu 002; Xinan Wang; Yuan Wang 001 (Microelectron. J., 2022)

A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling. - Xin Qiao; Jiahao Song; Xiyuan Tang; Haoyang Luo; Nanbing Pan; Xiaoxin Cui; Runsheng Wang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator. - Yisong Kuang; Xiaoxin Cui; Zilin Wang; Chenglong Zou; Yi Zhong; Kefei Liu 002; Zhenhui Dai; Dunshan Yu; Yuan Wang 001; Ru Huang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Unsupervised Learning of Spike-Timing-Dependent Plasticity Based on a Neuromorphic Implementation. - Yi Zhong; Zilin Wang; Xiaoxin Cui; Jian Cao 002; Yuan Wang 001 (AICAS, 2023)

An Efficient Spiking Neural Network Accelerator with Sparse Weight. - Zilin Wang; Yi Zhong; Youming Yang 002; Xiaoxin Cui; Yuan Wang 001 (BioCAS, 2023)

A Spiking Neural Network Accelerator based on Ping-Pong Architecture with Sparse Spike and Weight. - Zilin Wang; Yi Zhong; Xiaoxin Cui; Yisong Kuang; Yuan Wang 001 (ISCAS, 2023)

An Evaluation Method of the Anti-Modeling-Attack Capability of PUFs. - Yongliang Chen; Xiaole Cui; Yun Liu; Xiaoxin Cui (IEEE Trans. Inf. Forensics Secur., 2023)

Real-Time Target Tracking System With Spiking Neural Networks Implemented on Neuromorphic Chips. - Kefei Liu 002; Xiaoxin Cui; Xiang Ji; Yisong Kuang; Chenglong Zou; Yi Zhong; Kanglin Xiao; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array. - Xiaole Cui; Chen Wei; Xu Feng; Xiaoxin Cui (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Jiahao Song; Haoyang Luo; Xin'an Wang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

LRTransDet: A Real-Time SAR Ship-Detection Network with Lightweight ViT and Multi-Scale Feature Fusion. - Kunyu Feng; Li Lun; Xiaofeng Wang; Xiaoxin Cui (Remote. Sens., 2023)

An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning. - Yi Zhong; Zilin Wang; Xiaoxin Cui; Jian Cao 002; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Toward a Lossless Conversion for Spiking Neural Networks with Negative-Spike Dynamics. - Chenglong Zou; Xiaoxin Cui; Guang Chen; Yuanyuan Jiang; Yuan Wang 001 (Adv. Intell. Syst., 2023)

An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array. - Sunrui Zhang; Xiaole Cui; Feng Wei; Xiaoxin Cui (IEEE Trans. Computers, 2023)

A Hybrid Heterogeneous Neural Network Accelerator based on Systolic Array. - Zilin Wang; Yi Zhong; Guang Chen; Shuo Feng; Youming Yang 002; Xiaoxin Cui; Yuan Wang 001 (AICAS, 2024)

A Convolutional Spiking Neural Network Accelerator with the Sparsity-Aware Memory and Compressed Weights. - Hanqing Liu; Xiaole Cui; Sunrui Zhang; Mingqi Yin; Yuanyuan Jiang; Xiaoxin Cui (ASAP, 2024)

An Efficient Spiking Convolutional Architecture with Compressed Address Event Representation and Adaptive Delay Asynchronous Clocks. - Zhenhui Dai; Li Lun; Zilin Wang; Jiawei Wang; Kunyu Feng; Yuan Wang 001; Dunshan Yu; Xiaoxin Cui (BioCAS, 2024)

An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow. - Zhenhui Dai; Jiawei Wang; Yi Zhong; Kunyu Feng; Cheng Zhao; Yuanyuan Jiang; Peiyu Chen; Yuan Wang 001; Dunshan Yu; Xiaoxin Cui (ISCAS, 2024)

SPAT: FPGA-based Sparsity-Optimized Spiking Neural Network Training Accelerator with Temporal Parallel Dataflow. - Yuanyuan Jiang; Li Lun; Jiawei Wang; Mingqi Yin; Hanqing Liu; Zhenhui Dai; Xiaole Cui; Xiaoxin Cui (ISCAS, 2024)

A 16.41 TOPS/W CNN Accelerator with Event-Based Layer Fusion for Real-Time Inference. - Jiawei Wang; Li Lun; Zhenhui Dai; Yuanyuan Jiang; Xiaoxin Cui (ISCAS, 2024)

A High Energy-Efficiency Multi-core Neuromorphic Architecture for Deep SNN Training. - Mingjing Li; Huihui Zhou; Xiaofeng Xu; Zhiwei Zhong; Puli Quan; Xueke Zhu; Yanyu Lin; Wenjie Lin; Hongyu Guo; Junchao Zhang; Yunhao Ma; Wei Wang; et al. (CoRR, 2024)

A reconfigurable FPGA-based spiking neural network accelerator. - Mingqi Yin; Xiaole Cui; Feng Wei; Hanqing Liu; Yuanyuan Jiang; Xiaoxin Cui (Microelectron. J., 2024)

The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells. - Xiaole Cui; Mingqi Yin; Hanqing Liu; Xiaoxin Cui (ACM Trans. Design Autom. Electr. Syst., 2024)

The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice. - Yongliang Chen; Xiaole Cui; Xiaoxin Cui; Xing Zhang 002 (Microelectron. J., 2024)

Dy-MFNS-CAC: An Encoding Mechanism to Suppress the Crosstalk and Repair the Hard Faults in Rectangular TSV Arrays. - Chen Wei; Xiaole Cui; Xiaoxin Cui (IEEE Trans. Reliab., 2024)

OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support. - Qingyu Guo; Nanbing Pan; Xin Qiao; Xiaoxin Cui; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An eDRAM-Based Computing-in-Memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network. - Xin Qiao; Youming Yang 002; Chang Xue; Yandong He; Xiaoxin Cui; Song Jia; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

How the Brain Achieves Real-Time Vision: A Spiking Position Perception Model. - Kefei Liu 002; Jingjie Shang; Xiaoxin Cui; Chenglong Zou; Yisong Kuang; Kanglin Xiao; Yi Zhong; Yuan Wang 001 (IEEE Trans. Cogn. Dev. Syst., 2024)

A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations. - Kanglin Xiao; Xin Qiao; Xiaoxin Cui; Jiahao Song; Haoyang Luo; Xin'an Wang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

NeuroREC: A 28-nm Efficient Neuromorphic Processor for Radar Emitter Classification. - Zilin Wang; Zehong Ou; Yi Zhong; Youming Yang 002; Li Lun; Hufei Li; Jian Cao 002; Xiaoxin Cui; Song Jia; Yuan Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Marmotini: A Weight Density Adaptation Architecture With Hybrid Compression Method for Spiking Neural Network. - Zilin Wang; Yi Zhong; Zehong Ou; Youming Yang 002; Shuo Feng; Guang Chen; Xiaoxin Cui; Song Jia; Yuan Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Towards Effective and Sparse Adversarial Attack on Spiking Neural Networks via Breaking Invisible Surrogate Gradients. - Li Lun; Kunyu Feng; Qinglong Ni; Ling Liang; Yuan Wang 001; Ying Li 056; Dunshan Yu; Xiaoxin Cui (CVPR, 2025)

NeuroHexa: A 2D/3D-Scalable Model-Adaptive NoC Architecture for Neuromorphic Computing. - Yi Zhong; Zilin Wang; Yipeng Gao; Xiaoxin Cui; Xing Zhang 002; Yuan Wang 001 (DATE, 2025)

CROSSCUT: A Multi-Core Neuromorphic Accelerator Improving Resource-Utilization. - Youming Yang 002; Yi Zhong; Zilin Wang; Tao Zhang; Li Lun; Yingying Cui; Xiaoxin Cui; Song Jia; Yuan Wang 001 (ISCAS, 2025)

A Reconfigurable Digital Compute-In-Memory Heterogeneous Macro for Differential Frame Convolution and Spiking Neural Network. - Cheng Zhao; Li Lun; Zhenhui Dai; Haozhe Chen; Yingying Cui; Xiaoxin Cui (ISCAS, 2025)

HyNITA: A Neuromorphic Inference and Training Accelerator for Hybrid ANN-SNN Fusion Models. - Yi Zhong; Li Lun; Zilin Wang; Jinhao Ruan; Yipeng Gao; Xiaoxin Cui; Xing Zhang 002; Yuan Wang 001 (ISCAS, 2025)

Blockchain adoption and consumer privacy concerns in a platform supply chain with manufacturer competition. - Jing Yu; Xiaoxin Cui; Chi Zhou 001 (RAIRO Oper. Res., 2025)

PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm. - Yi Zhong; Yisong Kuang; Kefei Liu 002; Zilin Wang; Shuo Feng; Guang Chen; Youming Yang 002; Xiuping Cui; Qiankun Wang; Jian Cao 002; Song Jia; Yun Liang 001; et al. (IEEE J. Solid State Circuits, 2025)

Toward High-Accuracy and Low-Latency Spiking Neural Networks With Two-Stage Optimization. - Ziming Wang; Yuhao Zhang 007; Shuang Lian; Xiaoxin Cui; Rui Yan 005; Huajin Tang (IEEE Trans. Neural Networks Learn. Syst., 2025)