High-speed CMOS ring oscillators with low supply sensitivity. - Xiaoyan Gui; Michael M. Green (CICC, 2010)

Nonlinearities in frequency dividers. - Xiaoyan Gui; Michael M. Green (ECCTD, 2011)

Design and Implementation of a Circuit System for Neural Signal Detection. - Hua Dang; Xiao Li; Zhiming Chen 001; Xiaoyan Gui; Xinghua Wang; Shun'an Zhong (GreenCom/iThings/CPScom, 2013)

A Compensated Technique for 2.5-GHz Ring-Oscillator-Based PLL used in Wireless Transmission. - Hua Dang; Zicheng Liu 001; Xiaoyan Gui; Shun'an Zhong (GreenCom/iThings/CPScom, 2013)

A Whole Integrated System for Detection of Neural Signal and Wireless Transmission. - Hua Dang; Ruoyuan Qu; Zhiming Chen 001; Xiaoyan Gui; Xinghua Wang (GreenCom/iThings/CPScom, 2013)

Circuit Design of Analog Front-End for Neural Signal Detection. - Hua Dang; Lei Zhang; Zhiming Chen 001; Xiaoyan Gui; Xinghua Wang (GreenCom/iThings/CPScom, 2013)

Design and Implementation of a CMOS 1Gsps 5bit Flash ADC with Offset Calibration. - Shiwen Li; Hua Dang; Peng Gao; Xiaoyan Gui; Zhiming Chen 001; Xinghua Wang; Shun'an Zhong (GreenCom/iThings/CPScom, 2013)

Wireless circuits design for neural recording application. - Ruoyuan Qu; Na Liu; Zhe Guo; Xinghua Wang; Xiaoyan Gui (TSP, 2013)

Design of CML Ring Oscillators With Low Supply Sensitivity. - Xiaoyan Gui; Michael M. Green (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Modeling and design of a 0.8-30 GHz tunable inductor-less divide-by-2 frequency divider with digital frequency calibration. - Peng Gao; Zicheng Liu 001; Xiaoyan Gui (MWSCAS, 2015)

Design of a 12-bit 0.83 MS/s SAR ADC for an IPMI SoC. - Han Zhou; Xiaoyan Gui; Peng Gao (SoCC, 2015)

A Dual-Path Open-Loop CMOS Slew-Rate Controlled Output Driver with low PVT Variation. - Xiaoyan Gui; Kai Li; Xiaoli Wang; Li Geng (MWSCAS, 2018)

Design of A Low-Supply Sensitivity LC VCO with Complementary Varactors. - Bingjun Tang; Xiaoyan Gui; Li Geng (MWSCAS, 2018)

A Multi-Channel 1.52 µVrms Front End with Orthogonal Frequency Chopping for Neural Recording Applications. - Li Dong 007; Zhechong Lan; Xiaoyan Gui; Chengyang He; Youze Xin; Ken Li; Li Geng (APCCAS, 2019)

A Stacked 4×25 Gb/s Optical Receiver in 28 nm CMOS with 0.154 mW/Gb/s Power Efficiency. - Yihua Zhang; Zhuoqi Guo; Yang Xie; Dan Li 011; Shiquan Fan; Xiaoyan Gui; Li Geng (ISCAS, 2019)

A 16Gb/s Triple-Mode Driver in 0.18μm CMOS Technology. - Xiangwen Liu; Yihua Zhang; Chuangji Zhou; Dan Li 011; Xiaoyan Gui; Li Geng (ICTA, 2020)

A 100-Gb/s PAM-4 CTLE in 28-nm CMOS with Coarse-Fine Gain Adjustment. - Renjie Tang; Kanan Wang; Dan Li 011; Li Geng; Xiaoyan Gui (ICTA, 2020)

A Full-duplex Transceiver with Integrated Active Quasi-circulator Achieving Self-interference RF Cancellation over Wide Bandwidth. - Bingjun Tang; Jiangtao Xu; Xiaoyan Gui; Dan Li 011; Li Geng (ICTA, 2020)

A 112-Gb/s PAM-4 Linear Optical Receiver in 130-nm SiGe BiCMOS. - Dan Li 011; Shengwei Gao; Yongjun Shi; Xiaoyan Gui; Nan Qi; Zhiyong Li 014; Quan Pan 002; Patrick Chiang 001; Li Geng (ISCAS, 2020)

Low-Supply Sensitivity LC VCOs With Complementary Varactors. - Xiaoyan Gui; Bingjun Tang; Renjie Tang; Dan Li 011; Li Geng (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 720-mVpp 224-Gb/s PAM4 Optical Receiver with Multiple Peaking Techniques in 130-nm SiGe BiCMOS. - Qi Zhang; Xiongshi Luo; Zhenghao Li; Dongfan Xu; Siqiang Zhu; Leiming Wang; Zhenjiang Mao; Xiaoyan Gui; Dan Li 011; Hongyu Yu; Quan Pan 002 (APCCAS, 2021)

A 130-GBaud 2: 1 Analog Multiplexer in 130-nm SiGe BiCMOS. - Kanan Wang; Kuantian Guo; Haoran Yang; Renjie Tang; Zhen Zhao; Dan Li 011; Xiaoyan Gui (ICTA, 2021)

A 100GBaud Optical Receiver Front-End in 90nm SiGe BiCMOS. - Chuanhao Yu; Zhenyu Yin; Chenfan Cao; Shiti Huang; Quan Pan 002; Xiaoyan Gui; Li Geng; Dan Li 011 (ICTA, 2021)

A Low-Noise Stacked Differential Optical Receiver in 0.18-μm CMOS. - Wei Huang; Xiangwen Liu; Yongjun Shi; Dan Li 011; Bing Zhang 019; Xiaoyan Gui; Li Geng (MWSCAS, 2021)

A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array. - Li Dong 007; Yan Song; Yi Xie; Youze Xin; Ken Li; Xixin Jing; Bing Zhang 019; Xiaoyan Gui; Li Geng (Microelectron. J., 2021)

A 10/2.5-Gb/s Hyper-Supplied CMOS Low-Noise Burst-Mode TIA with Loud Burst Protection and Gearbox Automatic Offset Cancellation for XGS-PON. - Chen Tan; Wei Huang; Yonghui Fan; Jing Li; Chuanhao Yu; Wenbo Shi; Shiti Huang; Zhenyu Yin; Chenfan Cao; Lei Jing; Zhixiong Ren; Xiaoyan Gui; et al. (CICC, 2022)

A 54-68 GHz Power Amplifier With Improved Linearity and Efficiency in 40 nm CMOS. - Hamed Mosalam; Wenbo Xiao; Xiaoyan Gui; Dan Li 011; Quan Pan 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 12-Bit 20-kS/s 640-nW SAR ADC With a VCDL-Based Open-Loop Time-Domain Comparator. - Xiaochuan Zhou; Xiaoyan Gui; Marjan Gusev; Nevena Ackovska; Yanlong Zhang; Li Geng (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 28/56 Gb/s NRZ/PAM-4 Dual-Mode Transceiver in 28-nm CMOS. - Yukun He; Zhao Yuan; Kanan Wang; Renjie Tang; Yunxiang He; Dan Li 011; Li Geng; Xiaoyan Gui (ICTA, 2023)

A CMOS slew-rate controlled output driver with low process, voltage and temperature variations using a dual-path signal-superposition technique. - Xiaoyan Gui; Renjie Tang; Kai Li; Kanan Wang; Dan Li 011; Quan Pan 002; Li Geng (IET Circuits Devices Syst., 2023)

A 4×4 5-6GHz CMOS Wi-Fi Transceiver Front-End for Fiber-to-the-Room with Analog Beamforming Achieving 27dBm 1024 QAM MCS11 EIRP and -45dB EVM Floor. - Xin Lei; Xinhao Zheng; Yiqian Nie; Xinke Huang; Kun Fu; Yukun He; Xiaoyan Gui (CICC, 2024)

An Integrated Burst-Mode 2R Receiver Employing Fast Residual Offset Canceller for XGS-PON in 40-nm CMOS. - Yifei Xia; Shuaizhe Ma; Wanqing Zhao; Jia Li; Ruixuan Yang; Yuye Yang; Xi Liu; Feiyang Zhang; Jianyu Yang; Wenbo Shi; Lei Jing; Xiaoyan Gui; et al. (CICC, 2024)

A Low-Noise Power-Efficient Stacked Differential Transimpedance Amplifier in 0.18-μm CMOS. - Shuaizhe Ma; Xi Liu; Nianquan Ran; Yuye Yang; Yifei Xia; Ruixuan Yang; Binhao Wang; Yanlong Zhang; Xuhui Wang; Xiaoyan Gui; Li Geng; Dan Li (ICTA, 2024)

130 GBaud PAM-4 1-to-4 Analog Demultiplexer for Wireline and Optical Receivers in 130-nm SiGe. - Yu Su; Chenyao Cao; Bingyu Zhao; Renjie Tang; Shangjie Wei; Yukun He; Yuyan Lv; Xiaoyan Gui (ICTA, 2024)

Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS. - Shuaizhe Ma; Nianquan Ran; Xi Liu; Yifei Xia; Songqin Xu; Wei Huang; Chen Tan; Jing Li; Zhenyu Yin; Shaoheng Lin; Jianhua Pan; Zhe Chen; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

36.5 A Low-Latency 200Gb/s PAM-4 Heterogeneous Transceiver in 0.13μm SiGe BiCMOS and 28nm CMOS for Retimed Pluggable Optics. - Renjie Tang; Kanan Wang; Shuyi Xiang; Yu Su; Chenyao Cao; Yukun He; Xiaoyan Gui (ISSCC, 2025)

7.9 A 60Gb/s NRZ Burst-Mode CDR with Cross-Injection Locking and Flash Phase Detector Achieving 0.13ns Reconfiguration Time in 28nm CMOS. - Shangjie Wei; Renjie Tang; Chenyao Cao; Yu Su; Kanan Wang; Zhengyang Ye; Huanfa Sun; Kun Fu; Xiaoyan Gui (ISSCC, 2025)

A 0.92-pJ/b 112-Gb/s PAM-4 Transmitter With Bandwidth and Linearity Enhanced Quasi-Voltage-Mode Driver and Reconfigurable Three-Tap T/2-T Variable Fractional-Spaced FFE in 28-nm CMOS. - Kanan Wang; Renjie Tang; Shuyi Xiang; Yukun He; Yunxiang He; Xiaoyan Gui (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)