A 10BIT 30MSPS CMOS A/D converter for high performance video applications. - Jian Li; Jianyun Zhang; Bo Shen; Xiaoyang Zeng; Yawei Guo; Tingao Tang (ESSCIRC, 2005)

VLSI design of a high-speed RAS crypto-processor with reconfigurable architecture. - Yibo Fan; Xiaoyang Zeng; Zhang Zhang; Jun Chen; Qianling Zhang (ISSPA, 2005)

A high-performance platform-based SoC for information security. - Min Wu; Xiaoyang Zeng; Jun Han 003; Yongyi Wu; Yibo Fan (ASP-DAC, 2006)

A 1.8-V 22-mW 10-bit 30-MS/s Subsampling Pipelined CMOS ADC. - Jian Li; Xiaoyang Zeng; Lei Xie; Jun Chen; Jianyun Zhang; Yawei Guo (CICC, 2006)

A modified high-radix scalable Montgomery multiplier. - Yibo Fan; Xiaoyang Zeng; Yu Yu; Gang Wang; Qianling Zhang (ISCAS, 2006)

A new low cost and reconfigurable RSA crypto-processor. - Yongxin Ma; Xiaoyang Zeng; Min Wu; Chengshou Sun (ISCAS, 2006)

A new dual-field elliptic curve cryptography processor. - Yongyi Wu; Xiaoyang Zeng (ISCAS, 2006)

Adaptive bandwidth PLL with compact current mode filter. - Jiefeng Yan; Lei Xie; Xiaoyang Zeng; Tingao Tang (ISCAS, 2006)

A Low-cost and High-performance SoC Design for OMA DRM2 Applications. - Yehua Gu; Xiaoyang Zeng; Jun Han 003; Jia Zhao (ISCAS, 2007)

An Energy-Proportion Synchronization Method for IR-UWB Communications. - Jing Wang 220; Lang Mai; Yanjie Peng; Jun Han 003; Xiaoyang Zeng (ISCAS, 2007)

Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation. - Jia Zhao; Jun Han 003; Xiaoyang Zeng; Yunsong Deng (SiPS, 2007)

A Novel Five-Point Algorithm of Phase Noise Cancellation in DTMB. - Yun Chen 001; Xiaoyang Zeng; An Pan; Jing Wang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Robust Timing and Frequency Synchronization Scheme for DTMB System. - Jianming Wu; Yun Chen 001; Xiaoyang Zeng; Hao Min (IEEE Trans. Consumer Electron., 2007)

A low-cost cryptographic processor for security embedded system. - Ronghua Lu; Jun Han 003; Xiaoyang Zeng; Qing Li; Lang Mai; Jia Zhao (ASP-DAC, 2008)

A full-custom design of AES SubByte module with signal independent power consumption. - Liang Li; Jun Han 003; Xiaoyang Zeng; Jia Zhao (ISCAS, 2008)

Optimal frame synchronization for DVB-S2. - Li Qing; Xiaoyang Zeng; Chuan Wu; Yulong Zhang 001; Yunsong Deng; Jun Han 003 (ISCAS, 2008)

Tracking loop for IR-UWB communications in IEEE 802.15 multi-path channels. - Daxian Yun; Yanjie Peng; Jun Han 003; Xiaoyang Zeng (ISCAS, 2008)

Low-complexity two-stage timing acquisition scheme for UWB communications. - Yanjie Peng; Lang Mai; Xiaoyang Zeng (WTS, 2008)

A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications. - Jian Li; Xiaoyang Zeng; Lei Xie; Jun Chen; Jianyun Zhang; Yawei Guo (IEEE J. Solid State Circuits, 2008)

Low-cost reconfigurable VLSI architecture for fast fourier transform. - Hao Xiao; An Pan; Yun Chen 001; Xiaoyang Zeng (IEEE Trans. Consumer Electron., 2008)

A multi-task-oriented security processing architecture with powerful extensibility. - Dan Cao; Jun Han 003; Xiaoyang Zeng; Shi-ting Lu (ASP-DAC, 2009)

A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications. - Bo Xiang; Dan Bao; Shuangqu Huang; Xiaoyang Zeng (ASAP, 2010)

A flexible LDPC decoder architecture supporting two decoding algorithms. - Shuangqu Huang; Dan Bao; Bo Xiang; Yun Chen 001; Xiaoyang Zeng (ISCAS, 2010)

A 128/256-point pipeline FFT/IFFT processor for MIMO OFDM system IEEE 802.16e. - Simeng Li; Huxiong Xu; Wenhua Fan; Yun Chen 001; Xiaoyang Zeng (ISCAS, 2010)

A scalable and fault-tolerant routing algorithm for NoCs. - Zewen Shi; Kaidi You; Yan Ying; Bei Huang; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2010)

Robust and reliable frame synchronization method for DVB-S2 system. - Yulong Zhang 001; Xubin Chen; Wenhua Fan; Jun Han 003; Xiaoyang Zeng (WTS, 2010)

Optimized digital automatic gain control for DVB-S2 system. - Yulong Zhang 001; Jialin Cao; Chuan Wu; Jun Han 003; Xiaoyang Zeng (WTS, 2010)

A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue. - Yan Ying; Dan Bao; Zhiyi Yu; Xiaoyang Zeng; Yun Chen 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Programmable Architecture for Flexi-Mode QC-LDPC Decoder Supporting Wireless LAN/MAN Applications and Beyond. - Dan Bao; Bo Xiang; Rui Shen; An Pan; Yun Chen 001; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Low cost VLSI architecture of resisting long echo channel estimation for DTMB system. - Yunlong Ge; Huxiong Xu; Yun Chen 001; Yizhi Wang; Xiaoyang Zeng (IEEE Trans. Consumer Electron., 2010)

An efficient iterative frequency domain equalization for ATSC DTV receiver. - Chuan Wu; Dan Bao; Xiaoyang Zeng; Bo Shen (IEEE Trans. Consumer Electron., 2010)

An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes. - Bo Xiang; Rui Shen; An Pan; Dan Bao; Xiaoyang Zeng (IEEE Trans. Very Large Scale Integr. Syst., 2010)

An area-Efficient LDPC decoder for multi-standard with conflict resolution. - Changsheng Zhou; Yunlong Ge; Xubin Chen; Yun Chen 001; Xiaoyang Zeng (ASAP, 2011)

Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications. - Hong Chang; Wenxian Lu; Xu Cheng 002; Yawei Guo; Xiaoyang Zeng (ASICON, 2011)

A robust frame synchronization scheme for Broadband Power-line Communication. - Chen Chen 011; Yuebin Huang; Yizhi Wang; Yun Chen 001; Xiaoyang Zeng (ASICON, 2011)

A control scheme for a 65nm 32×32b 4-read 2-write register file. - Jun Han 003; Xingxing Zhang; Baoyu Xiong; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2011)

A channel estimator for LTE downlink mapped on a multi-core processor platform. - Maofei He; Jiajie Zhang; Wenhua Fan; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2011)

A NoC-based multi-core architecture for IEEE 802.11i CCMP. - Yang Li; Jun Han 003; Shuai Wang; Junbao Liu; Xiaoyang Zeng (ASICON, 2011)

A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters. - Li Li 038; Jun Ma 005; Yawei Guo; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2011)

Analysis of adaptive support-weight based stereo matching for hardware realization. - Junbao Liu; Shuai Wang; Yang Li; Jun Han 003; Xiaoyang Zeng (ASICON, 2011)

A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS. - Jun Ma 005; Yawei Guo; Li Li 038; Yue Wu; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2011)

A hardware/software co-design approach for multiple-standard video bitstream parsing. - Sha Shen; Huibo Zhong; Yibo Fan; Xiaoyang Zeng (ASICON, 2011)

A method of quadratic programming for mapping on NoC architecture. - Jiayi Sheng; Liulin Zhong; Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2011)

A security processor based on MIPS 4KE architecture. - Shuai Wang; Yang Li; Junbao Liu; Jun Han 003; Xiaoyang Zeng (ASICON, 2011)

Design of a single-ended cell based 65nm 32×32b 4R2W register file. - Baoyu Xiong; Xingxing Zhang; Jun Han 003; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2011)

Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs. - Yueming Yang; Heng Quan; Zewen Shi; Xiaoyang Zeng; Zhiyi Yu (ASICON, 2011)

A low power 1.0 GHz VCO in 65nm-CMOS LP-process. - Zhang Zhang 004; Zhiyi Yu; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2011)

A two-way parallel CAVLC encoder for 4K×2K H.264/AVC. - Huibo Zhong; Sha Shen; Yibo Fan; Xiaoyang Zeng (ASICON, 2011)

An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture. - Liulin Zhong; Jiayi Sheng; Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng; Dian Zhou (ASICON, 2011)

A high speed reconfigurable face detection architecture. - Weina Zhou; Yao Zou; Lin Dai; Xiaoyang Zeng (ASICON, 2011)

A 4.32 mm2 170mW LDPC decoder in 0.13μm CMOS for WiMax/Wi-Fi applications. - Dan Bao; Chuan Wu; Yan Ying; Yun Chen 001; Xiaoyang Zeng (ASP-DAC, 2011)

A reconfigurable and deadlock-free routing algorithm for 2D Mesh Network-on-Chip. - Zewen Shi; Yueming Yang; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2011)

A channel estimation scheme for Chinese DTTB system combating long echo and high doppler shift. - Yizhi Wang; Yun Chen 001; Yunlong Ge; Huxiong Xu; Xiaoyang Zeng (ISCAS, 2011)

Fault tolerant computing for stream DSP applications using GALS multi-core processors. - Zhiyi Yu; Zewen Shi; Xiaoyang Zeng (ISCAS, 2011)

Flexible and efficient FEC decoders supporting multiple transmission standards. - Yun Chen 001; Changsheng Zhou; Yuebin Huang; Shuangqu Huang; Xiaoyang Zeng (ISOCC, 2011)

A common flexible architecture for Turbo/LDPC codes. - Yuebin Huang; Chen Chen 011; Changsheng Zhou; Yun Chen 001; Xiaoyang Zeng (ISOCC, 2011)

A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder. - Jialiang Liu; Xinhua Chen; Yibo Fan; Xiaoyang Zeng (VLSI-SoC, 2011)

MUX-MCM based quantization VLSI architecture for H.264/AVC high profile encoder. - Jiang Ying; Xinhua Chen; Yibo Fan; Xiaoyang Zeng (VLSI-SoC, 2011)

A 4-way parallel CAVLC design for H.264/AVC 4Kx2K 60fps encoder. - Huibo Zhong; Sha Shen; Yibo Fan; Xiaoyang Zeng (IEICE Electron. Express, 2011)

Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC. - Yibo Fan; Xiaoyang Zeng; Satoshi Goto (IEICE Trans. Electron., 2011)

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs. - Zewen Shi; Xiaoyang Zeng; Zhiyi Yu (IEICE Trans. Inf. Syst., 2011)

Efficient Iterative Frequency Domain Equalization for Single Carrier System with Insufficient Cyclic Prefix. - Chuan Wu; Dan Bao; Xiaoyang Zeng; Yun Chen 001 (IEICE Trans. Commun., 2011)

An 847-955 Mb/s 342-397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 μ m CMOS. - Bo Xiang; Dan Bao; Shuangqu Huang; Xiaoyang Zeng (IEEE J. Solid State Circuits, 2011)

A low power ASIP for precision configurable FFT processing. - Yifan Bo; Jun Han 003; Yao Zou; Xiaoyang Zeng (APSIPA, 2012)

A single-routing layered LDPC decoder for 10Gbase-T Ethernet in 130nm CMOS. - Dan Bao; Xubin Chen; Yuebin Huang; Chuan Wu; Yun Chen 001; Xiaoyang Zeng (ASP-DAC, 2012)

A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder. - Huailu Ren; Yibo Fan; Xinhua Chen; Xiaoyang Zeng (ASP-DAC, 2012)

A 60mW baseband SoC for CMMB receiver. - Chuan Wu; Jialin Cao; Dan Bao; Yun Chen 001; Xiaoyang Zeng (ASP-DAC, 2012)

A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards. - Sha Shen; Weiwei Shen; Yibo Fan; Xiaoyang Zeng (ICME, 2012)

An improved coarse synchronization scheme in 3GPP LTE downlink OFDM systems. - Na Ding; Chen Chen 011; Wenhua Fan; Yun Chen 001; Xiaoyang Zeng (ISCAS, 2012)

Evaluating performance of manycore processors with various granularities considering yield and lifetime reliability. - Yueming Yang; Zewen Shi; Jianming Yu; Liulin Zhong; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2012)

A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost. - Yan Ying; Kaidi You; Liyang Zhou; Heng Quan; Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng (ISCAS, 2012)

A parallel CAVLC design for 4096×2160p encoder. - Huibo Zhong; Yibo Fan; Xiaoyang Zeng (ISCAS, 2012)

Task-binding based branch-and-bound algorithm for NoC mapping. - Liyang Zhou; Ming-e Jing; Liulin Zhong; Zhiyi Yu; Xiaoyang Zeng (ISCAS, 2012)

A multi-core mapping implementation of 3780-point FFT. - Enle Chen; Yun Chen 001; Yizhi Wang; Chen Chen 011; Xiaoyang Zeng (ISOCC, 2012)

A low-cost architecture for multi-mode Reed-Solomon decoder. - Yun Chen 001; Yuebin Huang; Wei Meng; Zhiyi Yu; Xiaoyang Zeng (ISOCC, 2012)

An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. - Zhiyi Yu; Kaidi You; Ruijin Xiao; Heng Quan; Peng Ou; Yan Ying; Haofan Yang 001; Ming-e Jing; Xiaoyang Zeng (ISSCC, 2012)

A Low Complexity Macroblock Layer Rate Control Scheme Base on Weighted-Window for H.264 Encoder. - Huibo Zhong; Sha Shen; Yibo Fan; Xiaoyang Zeng (MMM, 2012)

Fine Residual Carrier Frequency and Sampling Frequency Estimation in Wireless OFDM Systems - Chen Chen 011; Yun Chen 001; Xiaoyang Zeng (CoRR, 2012)

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. - Jun Han 003; Xingxing Zhang; Yi Li; Baoyu Xiong; Yuejun Zhang; Zhang Zhang 004; Zhiyi Yu; Xu Cheng 002; Xiaoyang Zeng (IEICE Electron. Express, 2012)

A Flexible Architecture for TURBO and LDPC Codes. - Yun Chen 001; Yuebin Huang; Chen Chen 011; Changsheng Zhou; Xiaoyang Zeng (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform. - Wenhua Fan; Chen Chen 011; Yun Chen 001; Zhiyi Yu; Xiaoyang Zeng (IEICE Trans. Commun., 2012)

An 8 × 4 Adaptive Hadamard Transform Based FME VLSI Architecture for 4 K × 2 K H.264/AVC Encoder. - Yibo Fan; Jialiang Liu; Dexue Zhang; Xiaoyang Zeng; Xinhua Chen (IEICE Trans. Electron., 2012)

A Fully Programmable Reed-Solomon Decoder on a Multi-Core Processor Platform. - Bei Huang; Kaidi You; Yun Chen 001; Zhiyi Yu; Xiaoyang Zeng (IEICE Trans. Inf. Syst., 2012)

A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms. - Shuangqu Huang; Xiaoyang Zeng; Yun Chen 001 (IEICE Trans. Inf. Syst., 2012)

A 64 Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4 K × 2 K Applications. - Weiwei Shen; Yibo Fan; Xiaoyang Zeng (IEICE Trans. Electron., 2012)

Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm. - Yuli Zhang; Jun Han 003; Xinqian Weng; Zhongzhu He; Xiaoyang Zeng (IEICE Trans. Electron., 2012)

A High Speed Reconfigurable Face Detection Architecture Based on AdaBoost Cascade Algorithm. - Weina Zhou; Lin Dai; Yao Zou; Xiaoyang Zeng; Jun Han 003 (IEICE Trans. Inf. Syst., 2012)

An Area-Efficient Reconfigurable LDPC Decoder with Conflict Resolution. - Changsheng Zhou; Yuebin Huang; Shuangqu Huang; Yun Chen 001; Xiaoyang Zeng (IEICE Trans. Electron., 2012)

A hardware-efficient variable-length FFT processor for low-power applications. - Yifan Bo; Renfeng Dou; Jun Han 003; Xiaoyang Zeng (APSIPA, 2013)

An ultra low-power and area-efficient baseband processor for WBAN transmitter. - Mengyuan Chen; Jun Han 003; Dabin Fang; Yao Zou; Xiaoyang Zeng (APSIPA, 2013)

Positionable wearable fall detection system for elderly assisted living applications. - Jie Cheng; Yun Chen 001; Wenxu Bao; Yuanzhou Hu; Na Ding; Xiaoyang Zeng (ASICON, 2013)

Design of a high throughput configurable variable-length FFT processor based on switch network architecture. - Renfeng Dou; Yifan Bo; Jun Han 003; Xiaoyang Zeng (ASICON, 2013)

Highly flexible WBAN transmit-receive system based on USRP. - Tianchan Guan; Jun Han 003; Xiaoyang Zeng (ASICON, 2013)

A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networks. - Jie Lin; Wei Zhou; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder. - Cong Liu 014; Weiwei Shen; Tianlong Ma; Yibo Fan; Xiaoyang Zeng (ASICON, 2013)

A fast 8×8 IDCT algorithm for HEVC. - Tianlong Ma; Cong Liu 014; Yibo Fan; Xiaoyang Zeng (ASICON, 2013)

An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP. - Weijing Shi; Yi Li; Jun Han 003; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2013)

A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor. - Biao Wang; Meng Zhang; Xu Cheng 002; Qi Feng; Xiaoyang Zeng (ASICON, 2013)

A fast multi-core virtual platform and its application on software development. - Zongyan Wang; Dexue Zhang; Xueqiu Yu; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

A high-throughput LDPC decoder for optical communication. - Di Wu 016; Yun Chen 001; Yuebin Huang; Yeong-Luh Ueng; Li-Rong Zheng 001; Xiaoyang Zeng (ASICON, 2013)

Low power design for FIR filter. - Gaowei Xu; Yao Zou; Jun Han 003; Xiaoyang Zeng (ASICON, 2013)

Efficient implementation of 3780-point FFT on a 16-core processor. - Haofan Yang 001; Kedong Chen; Shengqiong Xie; Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform. - Qing Zhang; Xueqiu Yu; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support. - Dexue Zhang; Xiaoyang Zeng; Zongyan Wang; Weike Wang; Xinhua Chen (ASICON, 2013)

A 2D mesh NoC with self-configurable and shared-FIFOs routers. - Wei Zhou; Jianming Yu; Jie Lin; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

H.264 video parallel decoder on a 24-core processor. - Shikai Zhu; Zheng Yu 001; Shile Cui; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs. - Yi Li; Xu Cheng 002; Yicheng Zhang; Weijing Shi; Jun Han 003; Xiaoyang Zeng (BioCAS, 2013)

A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms. - Shuai Wang; Jun Han 003; Yang Li; Yifan Bo; Xiaoyang Zeng (CICC, 2013)

An efficient multi-rate LDPC-CC decoder with layered decoding algorithm. - Yun Chen 001; Changsheng Zhou; Yuebin Huang; Xiaoyang Zeng (ICC, 2013)

Implementation and optimization of 3780-point FFT on multi-core system. - Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng; Jiayi Sheng; Haofan Yang 001 (ISCAS, 2013)

Time-Division-Multiplexer based routing algorithm for NoC system. - Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng; Liyang Zhou (ISCAS, 2013)

A high-throughput VLSI architecture for deblocking filter in HEVC. - Weiwei Shen; Qing Shang; Sha Shen; Yibo Fan; Xiaoyang Zeng (ISCAS, 2013)

A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs. - Yue Wu; Xu Cheng 002; Xiaoyang Zeng (ISCAS, 2013)

A 3.4dB NF k-band LNA in 65nm CMOS technology. - Jianfei Xu; Na Yan; Qiang Chen; Jianjun Gao; Xiaoyang Zeng (ISCAS, 2013)

A low power register file with asynchronously controlled read-isolation and software-directed write-discarding. - Zheng Yu 001; Jiajie Zhang; Xueqiu Yu; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2013)

A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array. - Peng Ou; Jiajie Zhang; Heng Quan; Yi Li; Maofei He; Zheng Yu 001; Xueqiu Yu; Shile Cui; Jie Feng; Shikai Zhu; Jie Lin; Ming-e Jing; et al. (ISSCC, 2013)

Algorithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC. - Yun Chen 001; Qiang Zhang; Yunlong Ge; Yuanzhou Hu; Jie Chen; Na Ding; Xiaoyang Zeng; Defeng Huang (MWSCAS, 2013)

Fine residual carrier frequency and sampling frequency estimation in wireless OFDM systems. - Chen Chen 011; Yun Chen 001; Na Ding; Qiang Zhang; Wenxu Bao; Yuanzhou Hu; Xiaoyang Zeng (MWSCAS, 2013)

Robustness Analysis of Mesh-Based Network-on-Chip Architecture under Flooding-Based Denial of Service Attacks. - Dabin Fang; Huikai Li; Jun Han 003; Xiaoyang Zeng (NAS, 2013)

A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC. - Sha Shen; Weiwei Shen; Yibo Fan; Xiaoyang Zeng (IEICE Electron. Express, 2013)

A 1.5 Gb/s Highly Parallel Turbo Decoder for 3GPP LTE/LTE-Advanced. - Yun Chen 001; Xubin Chen; Zhiyuan Guo; Xiaoyang Zeng; Defeng Huang (IEICE Trans. Commun., 2013)

A Unified Forward/Inverse Transform Architecture for Multi-Standard Video Codec Design. - Sha Shen; Weiwei Shen; Yibo Fan; Xiaoyang Zeng (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme. - Yue Wu; Xu Cheng 002; Xiaoyang Zeng (Microelectron. J., 2013)

An Ultra-Low Power QRS Complex Detection Algorithm Based on Down-Sampling Wavelet Transform. - Yao Zou; Jun Han 003; Xinqian Weng; Xiaoyang Zeng (IEEE Signal Process. Lett., 2013)

Accurate Sampling Timing Acquisition for Baseband OFDM Power-Line Communication in Non-Gaussian Noise. - Chen Chen 011; Yun Chen 001; Na Ding; Yizhi Wang; Jia-Chin Lin 001; Xiaoyang Zeng; Defeng David Huang (IEEE Trans. Commun., 2013)

Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform. - Jun Han 003; Shuai Wang; Wei Huang; Zhiyi Yu; Xiaoyang Zeng (IEEE Trans. Very Large Scale Integr. Syst., 2013)

An error-resilient wavelet-based ECG processor under voltage overscaling. - Mengyuan Chen; Jun Han 003; Yicheng Zhang; Yao Zou; Yi Li; Xiaoyang Zeng (BioCAS, 2014)

Acceleration of Naive-Bayes algorithm on multicore processor for massive text classification. - Lijun Zhou; Zhiyi Yu; Jie Lin; Shikai Zhu; Weijing Shi; Haijie Zhou; Kunpeng Song; Xiaoyang Zeng (ISIC, 2014)

A hardware-friendly method for rate-distortion optimization of HEVC intra coding. - Weiwei Shen; Yibo Fan; Leilei Huang; Jiali Li; Xiaoyang Zeng (VLSI-DAT, 2014)

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. - Yi Li; Liang Wen; Yuejun Zhang; Xu Cheng 002; Jun Han 003; Zhiyi Yu; Xiaoyang Zeng (IEICE Electron. Express, 2014)

Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability. - Liang Wen; Zhikui Duan; Yi Li; Xiaoyang Zeng (Microelectron. J., 2014)

An Efficient Multirate LDPC-CC Decoder With a Layered Decoding Algorithm for the IEEE 1901 Standard. - Yun Chen 001; Qichen Zhang; Di Wu 016; Changsheng Zhou; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 16-Core Processor With Shared-Memory and Message-Passing Communications. - Zhiyi Yu; Ruijin Xiao; Kaidi You; Heng Quan; Peng Ou; Zheng Yu 001; Maofei He; Jiajie Zhang; Yan Ying; Haofan Yang 001; Jun Han 003; Xu Cheng 002; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process. - Zheng Yu 001; Zhiyi Yu; Xueqiu Yu; Ningxi Liu; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture. - Renfeng Dou; Jun Han 003; Yifan Bo; Zhiyi Yu; Xiaoyang Zeng (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Single-Port SRAM-Based Transpose Memory With Diagonal Data Mapping for Large Size 2-D DCT/IDCT. - Qing Shang; Yibo Fan; Weiwei Shen; Sha Shen; Xiaoyang Zeng (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Exploration for energy-efficient ECC decoder of WBAN. - Tianchan Guan; Jun Han 003; Xiaoyang Zeng (ASICON, 2015)

A SRAM-saving two-stage storage strategy for the coefficients memories in HEVC encoders. - Leilei Huang; Wei Cheng; Xiaoyang Zeng; Yibo Fan (ASICON, 2015)

OFDM synchronization implementation based on Chisel platform for 5G research. - Ziqiang Li 004; Yun Chen 001; Xiaoyang Zeng (ASICON, 2015)

A flexible HEVC intra mode decision hardware for 8kx4k real time encoder. - YanHeng Lu; Wei Cheng; Leilei Huang; Xiaoyang Zeng; Yibo Fan (ASICON, 2015)

A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals. - Yi Ren; Jun Han 003; Zhiyi Yu; Sizhong Xuan; Xiaoyang Zeng (ASICON, 2015)

Motion artifact removal based on ICA for ambulatory ECG monitoring. - Shudong Tian; Jun Han 003; Jianwei Yang; Lijun Zhou; Xiaoyang Zeng (ASICON, 2015)

A SIMD multiplier-accumulator design for pairing cryptography. - Weizhen Wang; Jun Han 003; Jielin Wang; Xiaoyang Zeng (ASICON, 2015)

Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design. - Jielin Wang; Weizhen Wang; Jianwei Yang; Zhiyi Yu; Jun Han 003; Xiaoyang Zeng (ASICON, 2015)

Energy-efficient sub-threshold level shifter. - Liang Wen; Li Li 038; Haibo Wen; Xiaoyang Zeng (ASICON, 2015)

A low-cost SoC implementation of AES algorithm for bio-signals. - Zhicheng Xie; Jun Han 003; Jianwei Yang; Lijun Zhou; Xiaoyang Zeng (ASICON, 2015)

A configurable SoC design for information security. - Sizhong Xuan; Jun Han 003; Zhiyi Yu; Yi Ren; Xiaoyang Zeng (ASICON, 2015)

Iterative disparity voting based stereo matching algorithm and its hardware implementation. - Zhi Hu; Yibo Fan; Xiaoyang Zeng (ASP-DAC, 2015)

An area-efficient architecture for stochastic LDPC decoder. - Qichen Zhang; Yun Chen 001; Di Wu 016; Xiaoyang Zeng; Yeong-Luh Ueng (DSP, 2015)

A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application. - Wei Cheng; Yibo Fan; YanHeng Lu; Yize Jin; Xiaoyang Zeng (ISCAS, 2015)

Latency-optimized stochastic LDPC decoder for high-throughput applications. - Di Wu 016; Yun Chen 001; Qichen Zhang; Li-Rong Zheng 001; Xiaoyang Zeng; Yeong-Luh Ueng (ISCAS, 2015)

An implementation of turbo equalization using cyclic prefix in LTE downlink system. - Yun Chen 001; Qichen Zhang; Yuanzhou Hu; Na Ding; Xiaoyang Zeng (SiPS, 2015)

EM independent Gaussian approximate message passing and its application in OFDM impulsive noise mitigation. - Yun Chen 001; Yuanzhou Hu; Yizhi Wang; Xiaoyang Zeng; David Huang 001 (SoCC, 2015)

A High-Throughput Processor for Dual-Field Elliptic Curve Cryptography with Power Analysis Resistance. - Wei Li 131; Xiaoyang Zeng; Xiao Feng; Zibin Dai (UIC/ATC/ScalCom, 2015)

Non-binary digital calibration for split-capacitor DAC in SAR ADC. - Yawei Guo; Yue Wu; Dongdong Guo; Xu Cheng 002; Zhiyi Yu; Xiaoyang Zeng (IEICE Electron. Express, 2015)

A low cost architecture for high performance face detection. - Weina Zhou; Huafeng Wu; Xiaoyang Zeng (Microprocess. Microsystems, 2015)

A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT. - Gaowei Xu; Jun Han 003; Yao Zou; Xiaoyang Zeng (IEEE Signal Process. Lett., 2015)

A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs. - Yibo Fan; Leilei Huang; Yufeng Bai; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation. - Jun Han 003; Renfeng Dou; Lingyun Zeng; Shuai Wang; Zhiyi Yu; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform. - Yao Zou; Jun Han 003; Sizhong Xuan; Shan Huang 003; Xinqian Weng; Dabin Fang; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

In-Block Prediction-Based Mixed Lossy and Lossless Reference Frame Recompression for Next-Generation Video Encoding. - Yibo Fan; Qing Shang; Xiaoyang Zeng (IEEE Trans. Circuits Syst. Video Technol., 2015)

A 65 nm Cryptographic Processor for High Speed Pairing Computation. - Jun Han 003; Yang Li; Zhiyi Yu; Xiaoyang Zeng (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. - Xiaoyang Zeng; Yi Li; Yuejun Zhang; Shujie Tan; Jun Han 003; Xingxing Zhang; Zhang Zhang 004; Xu Cheng 002; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A low-cost and energy-efficient EEG processor for continuous seizure detection using wavelet transform and AdaBoost. - Shan Huang 003; Jun Han 003; Xin Li; Zongxian Yang; Xiaoyang Zeng (BioCAS, 2016)

Convergence-optimized variable node structure for stochastic LDPC decoder. - Qichen Zhang; Yun Chen 001; Di Wu 016; Xiaoyang Zeng; Yeong-Luh Ueng (ICASSP, 2016)

Quarter LCU based integer motion estimation algorithm for HEVC. - Qinwei Jiang; Leilei Huang; Yibo Fan; Xiaoyang Zeng (ICIP, 2016)

Neural network based seizure detection system using raw EEG data. - Tianchan Guan; Xiaoyang Zeng; Letian Huang; Tianchan Guan; Mingoo Seok (ISOCC, 2016)

Cryptographie coprocessor design for IoT sensor nodes. - Weizhen Wang; Jun Han 003; Zhicheng Xie; Shan Huang 003; Xiaoyang Zeng (ISOCC, 2016)

Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors. - Xu Cheng 002; Xiaoyang Zeng; Qi Feng (Microelectron. J., 2016)

An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor. - Jun Han 003; Yicheng Zhang; Shan Huang 003; Mengyuan Chen; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error. - Liang Wen; Xu Cheng 002; Shudong Tian; Haibo Wen; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier. - Liang Wen; Xu Cheng 002; Keji Zhou; Shudong Tian; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders. - Di Wu 016; Yun Chen 001; Qichen Zhang; Yeong-Luh Ueng; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A Combined Deblocking Filter and SAO Hardware Architecture for HEVC. - Weiwei Shen; Yibo Fan; Yufeng Bai; Leilei Huang; Qing Shang; Cong Liu 014; Xiaoyang Zeng (IEEE Trans. Multim., 2016)

Implementation of a pipeline division-free MMSE MIMO detector that support soft-input and soft-output. - Ziqiang Li 004; Liyu Lin; Yun Chen 001; Xiaoyang Zeng (APCC, 2017)

A configurable nonlinear operation unit for neural network accelerator. - Yujie Cai; Xin Li; Jun Han 003; Xiaoyang Zeng (ASICON, 2017)

A high utilization FPGA-based accelerator for variable-scale convolutional neural network. - Xin Li; Yujie Cai; Jun Han 003; Xiaoyang Zeng (ASICON, 2017)

Research of a reconfigurable coarse-grained cryptographic processing unit based on different operation similar structure. - Longmei Nan; Xiaoyang Zeng; Zhouchuang Wang; Yiran Du; Wei Li 131 (ASICON, 2017)

Fp2 arithmetic acceleration based on modified Barrett modular multiplication algorithm. - Yalong Pang; Ying Zhang; Jun Han 003; Xiaoyang Zeng (ASICON, 2017)

Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design. - Jianwei Yang; Weizhen Wang; Zhicheng Xie; Jun Han 003; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2017)

FPGA-based efficient implementation of SURF algorithm. - Ying Zhang; Yujie Huang; Jun Han 003; Xiaoyang Zeng (ASICON, 2017)

Extending memory capacity of neural associative memory based on recursive synaptic bit reuse. - Tianchan Guan; Xiaoyang Zeng; Mingoo Seok (DATE, 2017)

An efficient spherical video sampling scheme based on Cube model. - Yize Jin; Liming Wang; Qinwei Jiang; Xiaoyang Zeng; Yibo Fan (ICCE, 2017)

Instruction set extension and hardware acceleration for SVM application toward a vector processor. - Yalong Pang; Jun Han 003; Jianmin Zeng; Yujie Huang; Xiaoyang Zeng (ISOCC, 2017)

Recursive Binary Neural Network Learning Model with 2.28b/Weight Storage Requirement. - Tianchan Guan; Xiaoyang Zeng; Mingoo Seok (CoRR, 2017)

A multi-core-based heterogeneous parallel turbo decoder. - Jianmin Zeng; Chubin Wu; Zhang Zhang 004; Xin Cheng 001; Guangjun Xie; Jun Han 003; Xiaoyang Zeng; Zhiyi Yu (IEICE Electron. Express, 2017)

A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding. - Yibo Fan; Leilei Huang; Zheng Xie; Xiaoyang Zeng (IEICE Trans. Electron., 2017)

Sub-threshold level converter with internal supply feedback for multi-voltage applications. - Liang Wen; Haibo Wen; Xiaoyang Zeng (IET Circuits Devices Syst., 2017)

Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F2 and K-means Clustering for Power Reduction. - Keji Zhou; Xiaoyong Xue; Jianguo Yang; Xiaoxin Xu; Hangbing Lv; Mingyu Wang 001; Ming-e Jing; Wenjun Liu; Xiaoyang Zeng; Steve S. Chung; Jing Li; Ming Liu 022 (A-SSCC, 2018)

Dynamic Task Scheduler for Real Time Requirement in Cloud Computing System. - Yujie Huang; Quan Zhang; Yujie Cai; Ming-e Jing; Yibo Fan; Xiaoyang Zeng (ICA3PP (4), 2018)

Content adaptive tiling method based on user access preference for streaming panoramic video. - Zhengzhong Tu; Tongyu Zong; Xueliang Xi; Li Ai; Yize Jin; Xiaoyang Zeng; Yibo Fan (ICCE, 2018)

Panoramic video delivery based on Laplace compensation and Sphere-Markov probability model. - Tongyu Zong; Zhengzhong Tu; Li Ai; Xueliang Xi; Yize Jin; Xiaoyang Zeng; Yibo Fan (ICCE, 2018)

A High-Throughput QC-LDPC Decoder for Near-Earth Application. - Shixian Li; Qichen Zhang; Yun Chen 001; Xiaoyang Zeng (DSP, 2018)

MiniTracker: A Lightweight CNN-based System for Visual Object Tracking on Embedded Device. - Bingyi Zhang; Xin Li; Jun Han 003; Xiaoyang Zeng (DSP, 2018)

A Compact and Configurable Long Short-Term Memory Neural Network Hardware Architecture. - Kewei Chen; Leilei Huang; Minjiang Li; Xiaoyang Zeng; Yibo Fan (ICIP, 2018)

An Automatic Task Partition Method for Multi-core System. - Ming-e Jing; Yujie Huang; Yibo Fan; Xiaoyong Xue; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2018)

The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization. - Yujie Huang; Yujie Cai; Ming-e Jing; Jun Han 003; Yibo Fan; Xiaoyang Zeng (ISOCC, 2018)

Multi-mode Study of Deep Learning Applications in Acoustic Signal Processing. - Sheng Guan; Weicheng He; Wenjin Gu; Yuanzhao Hou; Yun Chen 001; Xiaoyang Zeng (SiPS, 2018)

A single-supply sub-threshold level shifter with an internal supply feedback loop for multi-voltage applications. - Longmei Nan; Xiaoyang Zeng; Wei Li 131; Zhouchuang Wang; Zibin Dai (IEICE Electron. Express, 2018)

A 15 W wireless power receiver with an improved full-wave synchronous rectifier. - Chubin Wu; Guangjun Xie; Zhang Zhang 004; Xin Cheng 001; Tairan Fei; Jianmin Zeng; Xiaoyang Zeng (IEICE Electron. Express, 2018)

Countering power analysis attacks by exploiting characteristics of multicore processors. - Jianwei Yang; Fan Dai; Jielin Wang; Jianmin Zeng; Zhang Zhang 004; Jun Han 003; Xiaoyang Zeng (IEICE Electron. Express, 2018)

A Hardware-Oriented IME Algorithm for HEVC and Its Hardware Implementation. - Yibo Fan; Leilei Huang; Bei Hao; Xiaoyang Zeng (IEEE Trans. Circuits Syst. Video Technol., 2018)

An Orthogonal Algorithm for Key Management in Hardware Obfuscation. - Jiawei Wang; Yuejun Zhang; Pengjun Wang; Zhicun Luan; Xiaoyong Xue; Xiaoyang Zeng; Qiaoyan Yu (AsianHOST, 2019)

Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications. - Yujie Cai; Keji Zhou; Xiaoyong Xue; Mingyu Wang; Xiaoyang Zeng (ASICON, 2019)

High throughput multi-code LDPC encoder for CCSDS standard. - Jinfou Xie; Shixian Li; Yun Chen 001; Qichen Zhang; Xiaoyang Zeng (ASICON, 2019)

Enhanced Recursive Residual Network for Single Image Super-Resolution. - Yi Zhang; Xiaoshan He; Ming-e Jing; Yibo Fan; Xiaoyang Zeng (ASICON, 2019)

A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis. - Riyong Zheng; Chenghao Wang 006; Jun Han 003; Xiaoyang Zeng (ASICON, 2019)

A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key. - Xiaoyong Xue; Jianguo Yang; Yuejun Zhang; Mingyu Wang 001; Hangbing Lv; Xiaoyang Zeng; Ming Liu 022 (A-SSCC, 2019)

A 3.01 mm2 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm. - Qichen Zhang; Yun Chen 001; Xiaoyang Zeng; Keshab K. Parhi; Borivoje Nikolic (A-SSCC, 2019)

A Skeleton-based Action Recognition System for Medical Condition Detection. - Jun Yin; Jun Han 003; Chenghao Wang 006; Bingyi Zhang; Xiaoyang Zeng (BioCAS, 2019)

Very Deep Residual Network for Image Matting. - Huan Tang; Yujie Huang; Ming-e Jing; Yibo Fan; Xiaoyang Zeng (ICIP, 2019)

Bayesian Face Recognition Approach Based on Feature Fusion. - Jingjing Liu 004; Donghui He; Xiaoyang Zeng; Mingyu Wang 001; Xianchao Xiu; Wanquan Liu; Hui Chen 007; Yuyao Xiao (ICNC-FSKD, 2019)

Acoustic Frequency Division Based on Active Metamaterial: An Experimental Demonstration of Acoustic Frequency Halving. - Ping Zhao; Junyi Wang; Xihan Gu; Kangzhou Suo; Yun Chen 001; Xiaoyang Zeng (IoTaaS, 2019)

A 32-Pixel IDCT-Adapted HEVC Intra Prediction VLSI Architecture. - Genwei Tang; Ming-e Jing; Xiaoyang Zeng; Yibo Fan (ISCAS, 2019)

A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement. - Zhiyuan Chen 002; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Xiaoyang Zeng; Rui Paulo Martins (ISSCC, 2019)

Dual Learning-based Video Coding with Inception Dense Blocks. - Chao Liu 027; Heming Sun; Junan Chen; Zhengxue Cheng; Masaru Takeuchi; Jiro Katto; Xiaoyang Zeng; Yibo Fan (PCS, 2019)

A Minimal Adder-oriented 1D DST-VII/DCT-VIII Hardware Implementation for VVC Standard. - Yibo Fan; Jiro Katto; Heming Sun; Xiaoyang Zeng; Yixuan Zeng (SoCC, 2019)

Fast QTMT Partition Decision Algorithm in VVC Intra Coding based on Variance and Gradient. - Junan Chen; Heming Sun; Jiro Katto; Xiaoyang Zeng; Yibo Fan (VCIP, 2019)

Adaptive CU Split Decision with Pooling-variable CNN for VVC Intra Encoding. - Genwei Tang; Ming-e Jing; Xiaoyang Zeng; Yibo Fan (VCIP, 2019)

A Micro-Code-Based Hardware Architecture of Integer Motion Estimation for HEVC. - Chenhao Gu; Leilei Huang; Xiaoyang Zeng; Yibo Fan (VLSI-SoC, 2019)

A Compact 32-Pixel TU-Oriented and SRAM-Free Intra Prediction VLSI Architecture for HEVC Decoder. - Yibo Fan; Genwei Tang; Xiaoyang Zeng (IEEE Access, 2019)

ManiDec: Manifold Constrained Low-Rank and Sparse Decomposition. - Jingjing Liu 004; Donghui He; Xiaoyang Zeng; Mingyu Wang 001; Xianchao Xiu; Wanquan Liu; Wenhong Li (IEEE Access, 2019)

Pixels and Panoramas: An Enhanced Cubic Mapping Scheme for Video /Image-Based Virtual-Reality Scenes. - Yibo Fan; Yize Jin; Zihao Meng; Xiaoyang Zeng (IEEE Consumer Electron. Mag., 2019)

A 24-bit sigma-delta ADC with configurable chopping scheme. - Li Li 038; Xu Cheng 002; Zhang Zhang 004; Jianmin Zeng; Xiaoyang Zeng (IEICE Electron. Express, 2019)

A Micro-Code-Based IME Engine for HEVC and Its Hardware Implementation. - Leilei Huang; Yibo Fan; Chenhao Gu; Xiaoyang Zeng (IEICE Trans. Electron., 2019)

Recursive Binary Neural Network Training Model for Efficient Usage of On-Chip Memory. - Tianchan Guan; Peiye Liu; Xiaoyang Zeng; Martha A. Kim; Mingoo Seok (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Real-Time and Hardware-Efficient Processor for Skeleton-Based Action Recognition With Lightweight Convolutional Neural Network. - Bingyi Zhang; Jun Han 003; Zhize Huang; Jianwei Yang; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory. - Tianchan Guan; Xiaoyang Zeng; Mingoo Seok (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction. - Liang Wen; Yuejun Zhang; Xiaoyang Zeng (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian Transmitter. - Pan Xue; Yilei Shen; Dan Fang; Chenyang Wang; Haijun Shao; Ting Yi; Xiaoyang Zeng; Zhiliang Hong (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Context Event Features and Event Embedding Enhanced Event Detection. - Xin Shi; Xiaoyang Zeng; Jie Wu 034; Mengshu Hou; Hao Zhu (ACAI, 2020)

Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit. - Yan Li 084; Xiaoyoung Zeng; Zhengqi Gao; Liyu Lin; Jun Tao 001; Jun Han 003; Xu Cheng 002; Mehdi B. Tahoori; Xiaoyang Zeng (DAC, 2020)

A Hardware Friendly Haze Removal Method and Its Implementation. - Minjiang Li; Mingxu Cui; Jun Chi; Xiaoyang Zeng; Ming-e Jing; Yibo Fan (ICCE, 2020)

A Learning-Based Low Complexity in-Loop Filter for Video Coding. - Chao Liu 027; Heming Sun; Jiro Katto; Xiaoyang Zeng; Yibo Fan (ICME Workshops, 2020)

Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers. - Xu Cheng 002; Jue Wang; Jun Han 003; Xiaoyang Zeng (ISCAS, 2020)

Single Image Dehazing using a Novel Histogram Tranformation Network. - Jun Chi; Mingjiang Li; Zihao Meng; Yibo Fan; Xiaoyang Zeng; Ming-e Jing (ISCAS, 2020)

Directly Obtaining Matching Points without Keypoints for Image Stitching. - Yujie Huang; Ming-e Jing; Yibo Fan; Xiaoyong Xue; Xiaoyang Zeng (ISCAS, 2020)

An Energy Harvesting System with Reconfigurable Piezoelectric Energy Harvester Array for IoT Applications. - Zhen Li; Zhiyuan Chen 002; Qiping Wan; Qin Kuai; Junrui Liang; Philip K. T. Mok; Xiaoyang Zeng (ISCAS, 2020)

A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance. - Jue Wang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (ISCAS, 2020)

A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm2 using Sneaking Current Suppression and Compensation Techniques. - Jianguo Yang; Xiaoyong Xue; Xiaoxin Xu; Hangbing Lv; Feng Zhang 014; Xiaoyang Zeng; Meng-Fan Chang; Ming Liu 022 (VLSI Circuits, 2020)

A Convolutional Neural Network-Based Low Complexity Filter. - Chao Liu 027; Heming Sun; Jiro Katto; Xiaoyang Zeng; Yibo Fan (CoRR, 2020)

A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. - Haozhe Zhu; Chixiao Chen; Shiwei Liu 002; Qiaosha Zou; Mingyu Wang 001; Lihua Zhang; Xiaoyang Zeng; Chuanjin Richard Shi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

A Highly Configurable 7.62GOP/s Hardware Implementation for LSTM. - Yibo Fan; Leilei Huang; Kewei Chen; Xiaoyang Zeng (IEICE Trans. Electron., 2020)

Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier With Capacitor Reuse for Input Power Adaptation. - Zhiyuan Chen 002; Man-Kay Law; Pui-In Mak; Xiaoyang Zeng; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. - Yan Li 084; Xu Cheng 002; Chiyu Tan; Jun Han 003; Yuanfu Zhao; Liang Wang 024; Tongde Li; Mehdi B. Tahoori; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture. - Guozhu Xin; Jun Han 003; Tianyu Yin; Yuchao Zhou; Jianwei Yang; Xu Cheng 002; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A High-Performance Stochastic LDPC Decoder Architecture Designed via Correlation Analysis. - Qichen Zhang; Yun Chen 001; Shixian Li; Xiaoyang Zeng; Keshab K. Parhi (IEEE Trans. Circuits Syst., 2020)

A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard. - Yibo Fan; Yixuan Zeng; Heming Sun; Jiro Katto; Xiaoyang Zeng (IEEE Trans. Circuits Syst. Video Technol., 2020)

QNet: An Adaptive Quantization Table Generator Based on Convolutional Neural Network. - Xiao Yan 006; Yibo Fan; Kewei Chen; Xulin Yu; Xiaoyang Zeng (IEEE Trans. Image Process., 2020)

Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications. - Yuanyuan Han; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques. - Jianwei Yang; Jun Han 003; Fan Dai; Weizhen Wang; Xiaoyang Zeng (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Knowledge Distillation for U-Net Based Image Denoising. - Wenshu Chen; Liyuan Peng; Yujie Huang; Ming-e Jing; Xiaoyang Zeng (ASICON, 2021)

An Efficient Markov Random Field Based Denoising Approach for Dynamic Vision Sensor. - Xi Cheng; Haozhe Zhu; Jingjing Liu 004; Mingyu Wang 001; Xiaoyang Zeng (ASICON, 2021)

A Multiplier-less Transform Architecture with the Diagonal Data Mapping Transpose Memory for The AVS3 Standard. - Zhijian Hao; Fa Xu; Guoqing Xiang; Peng Zhang 007; Xiaoyang Zeng; Yibo Fan (ASICON, 2021)

An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process. - Xianwu Hu; Dongyang Li; Yu Wang; Jiayun Feng; Zizhao Ma; Shaohao Wang; Tai Min; Xiaoyang Zeng; Yufeng Xie (ASICON, 2021)

Arbitrary Style Transfer via Learning to Paint in the Feature Domain. - Yujie Huang; Yixuan Liu; Ming-e Jing; Mingyu Wang; Xiaoyong Xue; Xiaoyang Zeng; Yibo Fan (ASICON, 2021)

Combining Max Pooling and ReLU Activation Function in Stochastic Computing. - Lixing Li; Deyang Chen; Xiaoyong Xue; Xiaoyang Zeng (ASICON, 2021)

A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process. - Jinrong Li; Jue Wang; Xu Cheng 002; Yicheng Zeng; Xiaoyang Zeng (ASICON, 2021)

A Heterogeneous HEVC Video Encoder System Based on Two-Level CPU-FPGA Computing Architecture. - Yudi Qiu; Jie Jiao; Yuxin Tang; Yanwei Liu; Jianyu Ren; Xiaoyang Zeng; Yibo Fan (ASICON, 2021)

A Fine-grained Sparse Neural Network Accelerator for Image Classification. - Hao Zhang; Aorui Gou; Yibo Fan; Xiaoyang Zeng (ASICON, 2021)

Small Object Detection in Aerial Images. - Ruoyu Zhang; Ming-e Jing; Yibo Fan; Xiaoyang Zeng (ASICON, 2021)

A High-Efficient and Configurable Hardware Accelerator for Convolutional Neural Network. - Hui Zhang; Zhaojie Li; Heqing Yang; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2021)

Intra-array Non-Idealities Modeling and Algorithm Optimization for RRAM-based Computing-in-Memory Applications. - Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Zhiwang Guo; Xiaoyong Xue; Xiaoyang Zeng (ASICON, 2021)

Mutli-level Regression Anchor-free Object Detection. - Yi Zhou; Ming-e Jing; Fa Xu; Yibo Fan; Xiaoyang Zeng (ASICON, 2021)

A Synthesizable 0.0060mm2 VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme. - Jue Wang; Zhenyu Yang; Jiawei Wang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (A-SSCC, 2021)

A-A KD: Attention and Activation Knowledge Distillation. - Aorui Gou; Chao Liu 027; Heming Sun; Xiaoyang Zeng; Yibo Fan (BigMM, 2021)

TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications. - Yan Li 084; Jun Han 003; Xiaoyang Zeng; Mehdi B. Tahoori (DATE, 2021)

Fast Object Detection in HEVC Intra Compressed Domain. - Liuhong Chen; Heming Sun; Jiro Katto; Xiaoyang Zeng; Yibo Fan (EUSIPCO, 2021)

Fast Style Transfer with High Shape Retention. - Yujie Huang; Yi Ling; Ming-e Jing; Xiaoyong Xue; Xiaoyang Zeng; Yibo Fan (ISCAS, 2021)

Decision Tree-Based Adaptive Reconfigurable Cache Scheme. - Wei Zhu 021; Xiaoyang Zeng (Algorithms, 2021)

An efficient non-convex total variation approach for image deblurring and denoising. - Jingjing Liu 004; Ruijie Ma; Xiaoyang Zeng; Wanquan Liu; Mingyu Wang 001; Hui Chen 007 (Appl. Math. Comput., 2021)

A Power and Area Efficient Lepton Hardware Encoder with Hash-based Memory Optimization. - Xiao Yan 006; Zhixiong Di; Bowen Huang; Minjiang Li; Wenqiang Wang; Xiaoyang Zeng; Yibo Fan (CoRR, 2021)

Learned Video Compression with Residual Prediction and Loop Filter. - Chao Liu 027; Heming Sun; Jiro Katto; Xiaoyang Zeng; Yibo Fan (CoRR, 2021)

A Reconfigurable 74-140Mbps LDPC Decoding System for CCSDS Standard. - Yun Chen 001; Jimin Wang; Shixian Li; Jinfou Xie; Qichen Zhang; Keshab K. Parhi; Xiaoyang Zeng (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Manifold constrained joint sparse learning via non-convex regularization. - Jingjing Liu 004; Xianchao Xiu; Xin Jiang; Wanquan Liu; Xiaoyang Zeng; Mingyu Wang 001; Hui Chen 007 (Neurocomputing, 2021)

Orthogonal obfuscation based key management for multiple IP protection. - Yuejun Zhang; Jiawei Wang; Pengjun Wang; Xiaoyong Xue; Xiaoyang Zeng (Integr., 2021)

High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications. - Keji Zhou; Xiaoyong Xue; Jianguo Yang; Xiaoxin Xu; Hangbing Lv; Ming-e Jing; Jing Li; Xiaoyang Zeng; Ming Liu 022 (IEEE J. Solid State Circuits, 2021)

A low-power twiddle factor addressing architecture for split-radix FFT processor. - Ming Liu 022; Ping Zhao; Tianshu Wu; Keshab K. Parhi; Xiaoyang Zeng; Yun Chen 001 (Microelectron. J., 2021)

Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC. - Jue Wang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (Microelectron. J., 2021)

An energy-efficient crypto-extension design for RISC-V. - Weizhen Wang; Jun Han 003; Xu Cheng 002; Xiaoyang Zeng (Microelectron. J., 2021)

A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor. - Yong-Liang Zhang; Qiang Li; Hui Zhang; Wei-Zhen Wang; Jun Han 003; Xiaoyang Zeng; Xu Cheng 002 (Microelectron. J., 2021)

Learned Image Compression With Separate Hyperprior Decoders. - Zhao Zan; Chao Liu 027; Heming Sun; Xiaoyang Zeng; Yibo Fan (IEEE Open J. Circuits Syst., 2021)

MC-LSTM: Real-Time 3D Human Action Detection System for Intelligent Healthcare Applications. - Jun Yin; Jun Han 003; Ruiqi Xie; Chenghao Wang 006; Xuyang Duan; Yitong Rong; Xiaoyang Zeng; Jun Tao 001 (IEEE Trans. Biomed. Circuits Syst., 2021)

Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology. - Yuanyuan Han; Tongde Li; Xu Cheng 002; Liang Wang 024; Jun Han 003; Yuanfu Zhao; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework. - Chiyu Tan; Yan Li 084; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications. - Keji Zhou; Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Deyang Chen; Yujie Huang; Ming-e Jing; Jun Han 003; Haidong Tian; Xiankui Xiong; Qi Liu 010; Xiaoyong Xue; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Unambiguous Direction-of-Arrival Estimation for Improved Scanning Efficiency in Subarray-Based Hybrid Array. - Ziyu Guo; Xiaodong Wang 001; Xiaoyang Zeng (IEEE Trans. Veh. Technol., 2021)

An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits. - Shaohang Chu; Yan Li 084; Xu Cheng 002; Xiaoyang Zeng (APCCAS, 2022)

An Approximate-Computing-Based Adaptive Equalizer for Polarization Mode Dispersion. - Liyu Lin; Junhui Wang; Xiaoyang Zeng; Yun Chen 001 (APCCAS, 2022)

A 1.8GΩ-Input-Impedance 0.15µV-Input-Referred-Ripple Chopper Amplifier with Local Positive Feedback and SAR-Assisted Ripple Reduction. - Tianxiang Qu; Qinjing Pan; Xiaoyang Zeng; Zhiliang Hong; Jiawei Xu 001 (CICC, 2022)

A 91.6% Peak Efficiency Time-Domain-Controlled Single-Inductor Triple-Output Step-Up Converter with ±7.5 to ±12V Bipolar Output Voltages. - Peng Cao; Danzhu Lu; Jiawei Xu 001; Xiaoyang Zeng; Zhiliang Hong (ESSCIRC, 2022)

A 130μW Three-Step DT Incremental Δ ∑ ADC Achieving 107.6dB DR and 99.3dB SNDR with Zoom and Extended-Range Counting. - Lairong Fang; Yijie Li; Yao Zhang; Shuwen Zhang; Xiaoyang Zeng; Zhiliang Hong; Jiawei Xu 001 (ESSCIRC, 2022)

No-Reference Quality Assessment of Variable Frame-Rate Videos Using Temporal Bandpass Statistics. - Qi Zheng 004; Zhengzhong Tu; Yibo Fan; Xiaoyang Zeng; Alan C. Bovik (ICASSP, 2022)

Learned Video Compression With Residual Prediction And Feature-Aided Loop Filter. - Chao Liu 027; Heming Sun; Xiaoyang Zeng; Yibo Fan (ICIP, 2022)

Blind Video Quality Assessment via Space-Time Slice Statistics. - Qi Zheng 004; Zhengzhong Tu; Zhijian Hao; Xiaoyang Zeng; Alan C. Bovik; Yibo Fan (ICIP, 2022)

A 3.1 Gbin/s advanced entropy coding hardware design for AVS3. - Yujie Cai; Wei Li; Xiaoyang Zeng; Yibo Fan; Peng Zhang 007; Guoqing Xiang; Haibing Yin (ISCAS, 2022)

Fast Intra Mode Decision for VVC Based on Histogram of Oriented Gradient. - Aorui Gou; Heming Sun; Jiro Katto; Tingting Li; Xiaoyang Zeng; Yibo Fan (ISCAS, 2022)

A High Area-Efficiency RRAM-Based Strong PUF with Multi-Entropy Source and Configurable Double-Read Process. - Xianwu Hu; Yu Wang; Jiayun Feng; Zizhao Ma; Xiaoyang Zeng; Yufeng Xie (ISCAS, 2022)

A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback Noise. - Min Li; Jue Wang; Xu Cheng 002; Xiaoyang Zeng (ISCAS, 2022)

A Low-latency Carrier Phase Recovery Hardware for Coherent Optical Communication. - Liyu Lin; Kaihui Wang; Yun Chen 001; Jianjun Yu; Xiaoyang Zeng (ISCAS, 2022)

A QP-adaptive Mechanism for CNN-based Filter in Video Coding. - Chao Liu 027; Heming Sun; Jiro Katto; Xiaoyang Zeng; Yibo Fan (ISCAS, 2022)

NIMBLE: A Neuromorphic Learning Scheme and Memristor Based Computing-in-Memory Engine for EMG Based Hand Gesture Recognition. - Fengshi Tian; Jingwen Jiang; Jinhao Liang; Zhiyuan Zhang; Jiahe Shi; Chaoming Fang; Hui Wu 010; Xiaoyong Xue; Xiaoyang Zeng (ISCAS, 2022)

A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors. - Jing Wang 220; Zhiyuan Chen 002; Junrui Liang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (ISCAS, 2022)

A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration. - Jiawei Wang; Jue Wang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (ISCAS, 2022)

A Multiple Charge Extractions and Multiple Precharge Interface Circuit for Piezoelectric Energy Harvesting. - Yi Yang; Zhiyuan Chen 002; Jingjing Liu 004; Ziyu Guo; Junmin Jiang; Xiaoyang Zeng (ISCAS, 2022)

An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators. - Baijie Zhang; Jue Wang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (ISCAS, 2022)

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. - Haozhe Zhu; Bo Jiao; Jinshan Zhang 006; Xinru Jia; Yunzhengmao Wang; Tianchan Guan; Shengcheng Wang; Dimin Niu; Hongzhong Zheng; Chixiao Chen; Mingyu Wang 001; Lihua Zhang; et al. (ISSCC, 2022)

Learning from the NN-based Compressed Domain with Deep Feature Reconstruction Loss. - Liuhong Chen; Heming Sun; Xiaoyang Zeng; Yibo Fan (VCIP, 2022)

A high accuracy and low complexity quality control method for image compression. - Xiao Yan 006; Zhangxin Gong; Wenqiang Wang; Xiaoyang Zeng; Yibo Fan (CoRR, 2022)

A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. - Keji Zhou; Xinru Jia; Chenyang Zhao 008; Xumeng Zhang; Guangjian Wu; Chen Mu; Haozhe Zhu; Yanting Ding; Chixiao Chen; Xiaoyong Xue; Xiaoyang Zeng; Qi Liu 010 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

An Efficient Low-Complexity Convolutional Neural Network Filter. - Chao Liu 027; Heming Sun; Jiro Katto; Xiaoyang Zeng; Yibo Fan (IEEE Multim., 2022)

An Attention Nested U-Structure Suitable for Salient Ship Detection in Complex Maritime Environment. - Weina Zhou; Ying Zhou; Xiaoyang Zeng (IEICE Trans. Inf. Syst., 2022)

A 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications. - Keji Zhou; Ruijun Lin; Zhiwang Guo; Yixuan Liu; Jingwen Jiang; Chenyang Zhao; Jinbei Fang; Xiaoxin Xu; Xiaoyong Xue; Xiaoyang Zeng (Microelectron. J., 2022)

Completely Blind Video Quality Evaluator. - Qi Zheng 004; Zhengzhong Tu; Xiaoyang Zeng; Alan C. Bovik; Yibo Fan (IEEE Signal Process. Lett., 2022)

Hardware-Efficient Beamspace Direction-of-Arrival Estimator for Unequal-Sized Subarrays. - Ziyu Guo; Weizhen Wang; Xiaodong Wang 001; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Piezoelectric Energy Harvesters: An Overview on Design Strategies and Topologies. - Jing Wang 220; Zhiyuan Chen 002; Zhen Li; Junmin Jiang; Junrui Liang; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Fast CABAC Hardware Design for Accelerating the Rate Estimation in HEVC. - Yujie Cai; Yibo Fan; Leilei Huang; Xiaoyang Zeng; Haibing Yin; Bing Zeng (IEEE Trans. Circuits Syst. Video Technol., 2022)

A High Throughput and Energy Efficient Lepton Hardware Encoder With Hash-Based Memory Optimization. - Xiao Yan 006; Zhixiong Di; Bowen Huang; Minjiang Li; Wenqiang Wang; Xiaoyang Zeng; Yibo Fan (IEEE Trans. Circuits Syst. Video Technol., 2022)

QA-Filter: A QP-Adaptive Convolutional Neural Network Filter for Video Coding. - Chao Liu 027; Heming Sun; Jiro Katto; Xiaoyang Zeng; Yibo Fan (IEEE Trans. Image Process., 2022)

Tear the Image Into Strips for Style Transfer. - Yujie Huang; Yuhao Liu 001; Ming-e Jing; Xiaoyang Zeng; Yibo Fan (IEEE Trans. Multim., 2022)

Obstacle Detection for Unmanned Surface Vehicles by Fusion Refinement Network. - Weina Zhou; Xinxin Huang; Xiaoyang Zeng (IEICE Trans. Inf. Syst., 2022)

Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation. - Siqi He; Hongyi Zhang; Mengjie Li; Haozhe Zhu; Chixiao Chen; Qi Liu 010; Xiaoyang Zeng (AICAS, 2023)

Performance Error Evaluation of gem5 Simulator for ARM Server. - Yudi Qiu; Shiyan Yi; Ming-e Jing; Xiankui Xiong; Dong Xu 015; Xuanpeng Zhu; Xiaoyang Zeng; Yibo Fan (ASICON, 2023)

A Decision-Based CORDIC Hardware for Arc Tangent Calculation. - Haoyu Wu; Liyu Lin; Haodong Sun; Xiaoyang Zeng; Yun Chen (ASICON, 2023)

GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications. - Zizhao Ma; Xianwu Hu; Gan Wen; Yihao Wang; Zeming Wang; Yukai Lin; Yu Wang; Yuhao Guo; Yanlei Li; Xingdong Liang; Xiaoyang Zeng; Yufeng Xie (A-SSCC, 2023)

Multi-Instance Bias Suppression for Enhanced Generalization in Breast Cancer Diagnosis : Harnessing Histopathological Big Data Insights. - Syed Attique Shah; Xiaoyang Zeng; Awais Ahmed; Shaheed Parvez; Rui Xi; Mengshu Hou (IEEE Big Data, 2023)

A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter. - Zhen Li; Zhiyuan Chen 002; Man-Kay Law; Sijun Du; Xu Cheng 002; Xiaoyang Zeng; Jun Han 003 (CICC, 2023)

A 2MHz-BW 96.8dB-SNDR 98dB-SNR CT-Zoom ADC With Residue Feedforward, Redundancy and Fully LMS-Based Calibration. - Yijie Li; Lairong Fang; Xiaoyang Zeng; Zhiliang Hong; Jiawei Xu 001 (ESSCIRC, 2023)

An Efficient Bundle Adjustment Approach for Stereo Visual Odometry with Pose Consensus. - Weili Jin; Xiaoyang Zeng; Ming-e Jing; Jingjing Liu 004; Mingyu Wang 001; Wenhong Li (ICCE, 2023)

Graph-Attention-Network-Based Cost Estimation Model in Materialized View Environment. - Daobing Zhu; Shu Huan Fan; Xiaoyang Zeng; Rui Xi; Mengshu Hou (ICPADS, 2023)

Denoising Method for Dynamic Vision Sensor Based on Two-Dimensional Event Density. - Yaoyi Chen; Yujie Huang; Feiqiang Li; Xiaoyang Zeng; Wenhong Li; Mingyu Wang 001 (ISCAS, 2023)

Fast VVC Intra Encoding for Video Coding for Machines. - Aorui Gou; Heming Sun; Xiaoyang Zeng; Yibo Fan (ISCAS, 2023)

Queue-based Spatiotemporal Filter and Clustering for Dynamic Vision Sensor. - Feiqiang Li; Yujie Huang; Yaoyi Chen; Xiaoyang Zeng; Wenhong Li; Mingyu Wang 001 (ISCAS, 2023)

A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation. - Zizhao Ma; Xianwu Hu; Yihao Wang; Gan Wen; Xiaoyang Zeng; Yufeng Xie (ISCAS, 2023)

A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications. - Deyang Chen; Zhiwang Guo; Jinbei Fang; Chenyang Zhao 008; Jingwen Jiang; Keji Zhou; Haidong Tian; Xiankui Xiong; Xiaoyong Xue; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

TSDN: Two-Stage Raw Denoising in the Dark. - Wenshu Chen; Yujie Huang; Mingyu Wang 001; Xiaolin Wu 001; Xiaoyang Zeng (IEEE Trans. Image Process., 2023)

LineDL: Processing Images Line-by-Line With Deep Learning. - Yujie Huang; Wenshu Chen; Liyuan Peng; Yuhao Liu 001; Mingyu Wang 001; Xiao-Ping (Steven) Zhang; Xiaoyang Zeng (IEEE Trans. Image Process., 2023)

Tag-Sharer-Fusion Directory: A Scalable Coherence Directory With Flexible Entry Formats. - Yudi Qiu; Jie Jiao; Xiaoyang Zeng; Yibo Fan (IEEE Trans. Parallel Distributed Syst., 2023)

ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application. - Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Xiaoyong Xue; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 1.8-GΩ Input-Impedance 0.15-μV Input-Referred-Ripple Chopper Amplifier With Local Positive Feedback and SAR-Assisted Ripple Reduction. - Tianxiang Qu; Qinjing Pan; Liheng Liu; Xiaoyang Zeng; Zhiliang Hong; Jiawei Xu 001 (IEEE J. Solid State Circuits, 2023)

A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications. - Yan Liu; Yan Li 084; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Tuning Range Extension Technique for Waveform-Shaping Single-Core CMOS Oscillators With No Dedicated Harmonic Tuning. - Hengyao Zhao; Chao Fan; Zhiyuan Chen 002; Pei Zheng; Xiaoyang Zeng; Zhiliang Hong (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Reconfigurable Multiple Transform Selection Architecture for VVC. - Zhijian Hao; Heming Sun; Guoqing Xiang; Peng Zhang 007; Xiaoyang Zeng; Yibo Fan (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance. - Xunming Zhang; Long Liu; Di Wang 042; Ruijun Lin; Heyong Yang; Xiaoxin Xu; Jianguo Yang; Guozhong Xing; Xiaoyong Xue; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices. - Zhiwang Guo; Deyang Chen; Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Yixuan Liu; Haidong Tian; Xiankui Xiong; Keji Zhou; Xiaoyong Xue; Qi Liu 010; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A novel fast intra algorithm for VVC based on histogram of oriented gradient. - Aorui Gou; Heming Sun; Chao Liu 027; Xiaoyang Zeng; Yibo Fan (J. Vis. Commun. Image Represent., 2023)

DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization. - Yan Li 084; Chao Chen; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Area-Efficient Processing Elements-Based Adaptive Loop Filter Architecture With Optimized Memory for VVC. - Zhijian Hao; Heming Sun; Sirui Li; Xiaoyang Zeng; Yibo Fan (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication. - Xianwu Hu; Yu Wang; Zizhao Ma; Gan Wen; Zeming Wang; Zhichao Lu; Yunlong Liu; Yanlei Li; Xingdong Liang; Xiaoyang Zeng; Yufeng Xie (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications. - Jingwen Jiang; Keji Zhou; Jinhao Liang; Fengshi Tian; Chenyang Zhao 008; Jianguo Yang; Xiaoyong Xue; Xiaoyang Zeng (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators. - Baijie Zhang; Jiawei Wang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications. - Lizhou Wu; Chenyang Zhao 008; Jingbo Wang; Xueru Yu; Shoumian Chen; Chen Li; Jun Han 003; Xiaoyong Xue; Xiaoyang Zeng (ASPDAC, 2024)

A Real-Time Optical-Flow-based SLAM FPGA Accelerator with Inter-Frame Similarity Exploitation and Correlation-Guided Mixed-Precision Flow Update. - Mengjie Li; Haozhe Zhu; Yiming Zhang; Siqi He; Qi Liu 010; Xiaoyang Zeng; Chixiao Chen (A-SSCC, 2024)

ST-BPTT: A Memory-efficient BPTT SNN Training Approach through Gradient-Contribution-Driven Time-Step Selection. - Jiajun Lu; Haozhe Zhu; Xiaoyang Zeng; Chixiao Chen (BioCAS, 2024)

COVER: A Comprehensive Video Quality Evaluator. - Chenlong He; Qi Zheng 004; Ruoxi Zhu; Xiaoyang Zeng; Yibo Fan; Zhengzhong Tu (CVPR Workshops, 2024)

ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test. - Hongyi Zhang; Haozhe Zhu; Siqi He; Mengjie Li; Chengchen Wang; Xiankui Xiong; Haidong Tian; Xiaoyang Zeng; Chixiao Chen (DATE, 2024)

A 1024-Neuron 1M-Synapse Event-Driven SNN Accelerator for DVS Applications. - Xi Cheng; Shu Cao; Shangmei Wang; Xiaoyang Zeng; Wenhong Li; Mingyu Wang 001 (ISCAS, 2024)

A Lossless Compression Algorithm with Hardware Implementation for Dynamic Vision Sensor. - Zewei Ding; Shangmei Wang; Yujie Cai; Xiaoyang Zeng; Wenhong Li; Mingyu Wang 001 (ISCAS, 2024)

Privacy-preserving with Flexible Autoencoder for Video Coding for Machines. - Aorui Gou; Heming Sun; Xiaoyang Zeng; Yibo Fan (ISCAS, 2024)

CTU-Level Adaptive Quantization Method Joint with GOP based Temporal Filter for Video Coding. - Chenlong He; Wei Li; Xiaoxiang Chen; Zhijian Hao; Chao Liu 027; Xiaoyang Zeng; Yibo Fan (ISCAS, 2024)

A Single-Stage Four-Phase Dual-Output Regulating Rectifier With Ultrafast Transient Response Using Double-Frequency Current-Wave Modulation. - Weiyan Li; Xianren Hao; Xiaguang Li; Yan Ma; Jingjing Liu 004; Huaxi Zhang 003; Xiaoyang Zeng; Zhiyuan Chen 002 (ISCAS, 2024)

A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder. - Mengjie Li; Hongyi Zhang; Siqi He; Haozhe Zhu; Hao Zhang; Jinglei Liu; Jiayuan Chen; Zhenping Hu; Xiaoyang Zeng; Chixiao Chen (ISCAS, 2024)

A Semi-Folded Based High-Power-Efficiency FFT for Frequency Offset Estimate. - Liyu Lin; Jingguo Wu; Xiaoyang Zeng; Yun Chen (ISCAS, 2024)

Hardware Acceleration of Phase and Gain Control for Analog Beamforming. - Xinhao Mao; Ziyu Guo; Jun Han 003; Bo Hu 002; Xiaoyang Zeng (ISCAS, 2024)

GauSPU: 3D Gaussian Splatting Processor for Real-Time SLAM Systems. - Lizhou Wu; Haozhe Zhu; Siqi He; Jiapei Zheng; Chixiao Chen; Xiaoyang Zeng (MICRO, 2024)

Prompt-Eng: Healthcare Prompt Engineering: Revolutionizing Healthcare Applications with Precision Prompts. - Awais Ahmed; Mengshu Hou; Rui Xi; Xiaoyang Zeng; Syed Attique Shah (WWW (Companion Volume), 2024)

GATe: Streamlining Memory Access and Communication to Accelerate Graph Attention Network With Near-Memory Processing. - Shiyan Yi; Yudi Qiu; Lingfei Lu; Guohao Xu; Yong Gong; Xiaoyang Zeng; Yibo Fan (IEEE Comput. Archit. Lett., 2024)

Multi-granularity prior networks for uncertainty-informed patient-specific quality assurance. - Xiaoyang Zeng; Qizhen Zhu; Awais Ahmed; Muhammad Hanif 008; Mengshu Hou; Qiu Jie; Rui Xi; Syed Attique Shah (Comput. Biol. Medicine, 2024)

Advancing plant disease classification: A robust and generalized approach with transformer-fused convolution and Wasserstein domain adaptation. - Muhammad Hanif Tunio; Jian Ping Li 002; Xiaoyang Zeng; Awais Ahmed; Syed Attique Shah; Hisam-Uddin Shaikh; Ghulam Ali Mallah; Imam Abdullahi Yahya (Comput. Electron. Agric., 2024)

FSS: algorithm and neural network accelerator for style transfer. - Yi Ling; Yujie Huang; Yujie Cai; Zhaojie Li; Mingyu Wang; Wenhong Li; Xiaoyang Zeng (Sci. China Inf. Sci., 2024)

STCC-Filter: A space-time-content correlation-based noise filter with self-adjusting threshold for event camera. - Mengjie Li; Yujie Huang; Mingyu Wang; Wenhong Li; Xiaoyang Zeng (Signal Process. Image Commun., 2024)

FAVER: Blind quality prediction of variable frame rate videos. - Qi Zheng 004; Zhengzhong Tu; Pavan C. Madhusudana; Xiaoyang Zeng; Alan C. Bovik; Yibo Fan (Signal Process. Image Commun., 2024)

KBStyle: Fast Style Transfer Using a 200 KB Network With Symmetric Knowledge Distillation. - Wenshu Chen; Yujie Huang; Mingyu Wang 001; Xiaolin Wu 001; Xiaoyang Zeng (IEEE Trans. Image Process., 2024)

Angular Parameter Estimation for Incoherently Distributed Sources With Single RF Chain. - Ziyu Guo; Tao Yang 008; Peng Chen 018; Jun Han 003; Xiaoyang Zeng; Bo Hu 002 (IEEE Trans. Signal Process., 2024)

CCTSS: The Combination of CNN and Transformer with Shared Sublayer for Detection and Classification. - Aorui Gou; Jingjing Liu 004; Xiaoxiang Chen; Xiaoyang Zeng; Yibo Fan (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Meta-knowledge guided Bayesian optimization framework for robust crop yield estimation. - Muhammad Hanif Tunio; Jian Ping Li 002; Xiaoyang Zeng; Faijan Akhtar; Syed Attique Shah; Awais Ahmed; Yu Yang; Md Belal Bin Heyat (J. King Saud Univ. Comput. Inf. Sci., 2024)

Examining the role of tap cell in suppressing single event transient effect in 28-nm CMOS technology. - Chenyu Zhang; Yan Li 084; Wenfa Zhan; Wenping Geng; Ting Liang; Xiaoyang Zeng (Microelectron. J., 2024)

An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition. - Yongliang Zhang; Yitong Rong; Xuyang Duan; Zhen Yang; Qiang Li; Ziyu Guo; Xu Cheng 002; Xiaoyang Zeng; Jun Han 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Multimode Neuromorphic Vision Sensor With Improved Brightness Measurement Performance by Pulse Coding Method. - Zewei Ding; Qijuan Wu; Mingyu Wang 001; Jingjing Liu 004; Xiaoyang Zeng; Wenhong Li; Wei Huang; Zhi Liu 004; Xiao-Ping Zhang 002 (IEEE Internet Things J., 2024)

MED-Prompt: A novel prompt engineering framework for medicine prediction on free-text clinical notes. - Awais Ahmed; Xiaoyang Zeng; Rui Xi; Mengshu Hou; Syed Attique Shah (J. King Saud Univ. Comput. Inf. Sci., 2024)

Moving object detection in gigapixel-level videos using manifold sparse representation. - Jingjing Liu 004; Manlong Feng; Dongzhou Gu; Xiaoyang Zeng; Wanquan Liu; Xianchao Xiu (Multim. Tools Appl., 2024)

A 107.6 dB-DR Three-Step Incremental ADC for Motion-Tolerate Biopotential Signals Recording. - Lairong Fang; Shuwen Zhang; Yijie Li; Shunmin Wu; Xiaoyang Zeng; Zhiliang Hong; Jiawei Xu 001 (IEEE Trans. Biomed. Circuits Syst., 2024)

A Compact 0.1-1.95 GHz, 1.5 dB NF LNTA Based on Cascode Inverters. - Cong Tao; Jiangli Huang; Liangbo Lei; Yumei Huang; Zhiliang Hong; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Gem5Tune: A Parameter Auto-Tuning Framework for Gem5 Simulator to Reduce Errors. - Yudi Qiu; Tao Huang; Yuxin Tang; Yanwei Liu; Yang Kong; Xulin Yu; Xiaoyang Zeng; Yibo Fan (IEEE Trans. Computers, 2024)

SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure. - Yuanyuan Han; Xu Cheng 002; Xiaoyong Xue; Jun Han 003; Jiawei Xu 001; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique. - Jiawei Wang; Zhao Gao; Xu Cheng 002; Jue Wang; Zhen Li; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Trident-CIM: A LUT-Based Compute-in-Memory Macro With Trident Read Bit-Line and Partial Product Pruning. - Haozhe Zhu; Hongyi Zhang; Siqi He; Mengjie Li; Xiaoyang Zeng; Chixiao Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Fast Transform Kernel Selection Based on Frequency Matching and Probability Model for AV1. - Zhijian Hao; Heming Sun; Guohao Xu; Jiaming Liu; Xiankui Xiong; Xuanpeng Zhu; Xiaoyang Zeng; Yibo Fan (IEEE Trans. Broadcast., 2024)

Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier and Switched-PEH DC-DC for MPPT. - Zhen Li; Jing Wang 220; Man-Kay Law; Sijun Du; Junrui Liang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng; Zhiyuan Chen 002 (IEEE J. Solid State Circuits, 2024)

IMA-BLC: Iterative Median-Averaged Adaptive Black-Level Correction Method. - Yaoyi Chen; Yujie Huang; Mingyu Wang 001; Wenhong Li; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Low-Power, Compact, 0.1-5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR. - Cong Tao; Liangbo Lei; Chaoyang Zheng; Yumei Huang; Zhiliang Hong; Xiaoyang Zeng (IEEE J. Solid State Circuits, 2024)

A 28-nm 36 Kb SRAM CIM Engine With 0.173 μm2 4T1T Cell and Self-Load-0 Weight Update for AI Inference and Training Applications. - Chenyang Zhao 008; Jinbei Fang; Xiaoli Huang; Deyang Chen; Zhiwang Guo; Jingwen Jiang; Jiawei Wang; Jianguo Yang; Jun Han 003; Peng Zhou 021; Xiaoyong Xue; Xiaoyang Zeng (IEEE J. Solid State Circuits, 2024)

SLAM-CIM: A Visual SLAM Backend Processor With Dynamic-Range-Driven-Skipping Linear-Solving FP-CIM Macros. - Mengjie Li; Haozhe Zhu; Siqi He; Hongyi Zhang; Jie Liao; Danfeng Zhai; Chixiao Chen; Qi Liu 010; Xiaoyang Zeng; Ninghui Sun; Ming Liu 022 (IEEE J. Solid State Circuits, 2024)

A High Compression Efficiency Hardware Encoder for Intra and Inter Coding With 4K@30fps Throughput. - Guohao Xu; Leilei Huang; Zhijian Hao; Wei Li 257; Shiyan Yi; Xiaoyang Zeng; Yibo Fan (IEEE Trans. Circuits Syst. Video Technol., 2024)

A 1024-Spin Scalable Ising Machine With Capacitive Coupling and Progressive Annealing Method for Combination Optimization Problems. - Yixuan Liu; Zhongze Han; Qiqiao Wu; Honghu Yang; Yue Cao; Yongkang Han; Haijun Jiang; Xiaoyong Xue; Jianguo Yang; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Hi-NeRF: A Multicore NeRF Accelerator With Hierarchical Empty Space Skipping for Edge 3-D Rendering. - Lizhou Wu; Haozhe Zhu; Jiapei Zheng; Mengjie Li; Yinuo Cheng; Qi Liu 010; Xiaoyang Zeng; Chixiao Chen (IEEE Trans. Very Large Scale Integr. Syst., 2024)

ANS-LIC: A High-Throughput Parallel Hardware Implementation of ANS for Learned Imagination Codecs. - Shiyan Yi; Guohao Xu; Peng Zhang; Boyuan Shan; Xiaolong Xu; Yanheng Lu; Zihao Liu; Xiaoyang Zeng; Yibo Fan (DCC, 2025)

Penta Interlocking Dual Ports 14T SRAM with Inside-Bit interleaving Layout Isolation for Soft Error Recovery. - Xu Luo; Yuanyuan Han; Xu Cheng 002; Xiaoyang Zeng (ISCAS, 2025)

DS-HPPO Deep Reinforcement Learning for Optimal DVFS Control on an Image Signal Processor. - Yang Du; Wenhong Li; Xiaoyang Zeng (IEEE Access, 2025)

A novel transformers-based external attention framework for breast cancer diagnosis. - Rui Xi; Awais Ahmed; Xiaoyang Zeng; Mengshu Hou (Biomed. Signal Process. Control., 2025)

Enhancing multimodal medical image analysis with Slice-Fusion: A novel fusion approach to address modality imbalance. - Awais Ahmed; Xiaoyang Zeng; Rui Xi; Mengshu Hou; Syed Attique Shah (Comput. Methods Programs Biomed., 2025)

A Hardware-Friendly Lightweight Partition Decision Algorithm for VVC Intra and Inter Coding. - Zhao Zan; Leilei Huang; Shushi Chen; Xiaoyang Zeng; Yibo Fan (IEEE Signal Process. Lett., 2025)

Tensor Low-Rank Approximation via Plug-and-Play Priors for Anomaly Detection in Remote Sensing Images. - Jingjing Liu 004; Manlong Feng; Xianchao Xiu; Xiaoyang Zeng; Jianhua Zhang (IEEE Trans. Instrum. Meas., 2025)

MATCNN: Infrared and Visible Image Fusion Method Based on Multiscale CNN With Attention Transformer. - Jingjing Liu 004; Li Zhang; Xiaoyang Zeng; Wanquan Liu; Jianhua Zhang (IEEE Trans. Instrum. Meas., 2025)

MATCNN: Infrared and Visible Image Fusion Method Based on Multi-scale CNN with Attention Transformer. - Jingjing Liu 004; Li Zhang; Xiaoyang Zeng; Wanquan Liu; Jianhua Zhang (CoRR, 2025)

Light-CIM: A Lightweight ADC/DAC-Fewer RRAM CIM DNN Accelerator With Fully Analog Tiles and Nonideality-Aware Algorithm for Consumer Electronics. - Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Xiaoyong Xue; Xiaoyang Zeng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Efficient and Robust Sparse Linear Discriminant Analysis for Data Classification. - Jingjing Liu 004; Manlong Feng; Xianchao Xiu; Wanquan Liu; Xiaoyang Zeng (IEEE Trans. Emerg. Top. Comput. Intell., 2025)

An Interpolation-Free Fractional Motion Estimation Algorithm and Hardware Implementation for VVC. - Shushi Chen; Leilei Huang; Zhao Zan; Xiaoyang Zeng; Yibo Fan (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Enhancing Efficiency in Piezoelectric Energy Harvesting: Collaborative-Flip Synchronized Switch Harvesting on Capacitors Rectifier and Multioutput DC-DC Converters Utilizing Shared Capacitors. - Jing Wang 220; Yi Yang; Zhen Li; Sijun Du; Xinling Yue; Xun Liu; Jun Han 003; Xiaoyang Zeng; Zhiyuan Chen 002 (IEEE J. Solid State Circuits, 2025)

Affine Motion Estimation Hardware Implementation With 51.7%/67.5% Internal Bandwidth Reduction for Versatile Video Coding. - Shushi Chen; Leilei Huang; Zhao Zan; Zhijian Hao; Hao Zhang 126; Xiaoxiang Chen; Minge Jing; Xiaoyang Zeng; Yibo Fan (IEEE Trans. Circuits Syst. Video Technol., 2025)

A 2 MHz Bandwidth TMR-Based Contactless Current Sensor With Ping-Pong Auto-Zeroing and SAR-Assisted Offset Calibration. - Tianxiang Qu; Tian Dong; Wenhui Qin; Yaohua Pan; Yun Sheng; Zhiliang Hong; Xiaoyang Zeng; Jiawei Xu 001 (IEEE J. Solid State Circuits, 2025)

Nighttime Glare Removal for Consumer Electronics via Latent Space Transformation and Feature-Enhanced Attention Mechanism. - Jiazheng Lian; Jiaming Liu; Ming-e Jing; Xiaoyang Zeng; Zherong Liu; Jun Zhou 017; Yibo Fan (IEEE Trans. Consumer Electron., 2025)

High Signal-to-Noise Ratio and High-Sensitivity 4-D LiDAR Imaging Receiver. - Jianping Guo; Zhengping Gao; Xiaoyang Zeng; Wenhong Li; Mingyu Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

An FPGA-Based Event-Driven SNN Accelerator for DVS Applications With Structured Sparsity and Early-Stop. - Xi Cheng; Shu Cao; Shangmei Wang; Mingyu Wang 001; Wenhong Li; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Defective Pixel Corrector for Line Scan and Area Scan Image Sensors. - Liyuan Peng; Yujie Huang; Mingyu Wang 001; Wenhong Li; Minge Jing; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Principle-Guided Verilog Optimization: IP-Safe Knowledge Transfer via Local-Cloud Collaboration. - Jing Wang; Zheng Li; Lei Li; Fan He; Liyu Lin; Yao Lai; Yan Li; Xiaoyang Zeng; Yufeng Guo (CoRR, 2025)

A Continuous-Time Incremental ΣΔ ADC with Extended Counting Technique. - Tingting Wei; Zhu Yuan; Qiong Wang; Xiaoyang Zeng (Circuits Syst. Signal Process., 2025)

A 153.4 dB-DR PPG Recording IC With Extended Counting and Hardware Reuse. - Tingting Wei; Hang Chen; Jiahui Lai; Jinhua Ni; Xiaoyang Zeng; Zhiliang Hong (IEEE Trans. Biomed. Circuits Syst., 2025)

A Hybrid Buck-or-Boost Converter for Fast-Transient and Wide-Voltage-Range Applications With Continuous Output Delivery Current. - Junyi Ruan; Junmin Jiang; Chenzhou Ding; Kai Yuan; Ka Nang Leung; Zhiyuan Chen 002; Xiaoyang Zeng; Xun Liu (IEEE J. Solid State Circuits, 2025)

EF-CIM: An Endurance Friendly CIM Accelerator Using Embedded NVM With Bit-Aware Wear Leveling for Efficient Light-Weight On-Chip Training in Edge Devices. - Zhiwang Guo; Jingwen Jiang; Deyang Chen; Jinbei Fang; Jianguo Yang; Jun Han 003; Xiaoyong Xue; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Enhancing All-to-All RRAM Ising Machines With Randomized Granular Update Strategies for Solving Combinatorial Optimization Problems. - Yixuan Liu; Qiqiao Wu; Honghu Yang; Chengshuo Yu; Keji Zhou; Yu Jiang; Haijun Jiang; Hailan Yi; Xiaoyong Xue; Jianguo Yang; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)