A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell. - Ji Zhang 001; Yiqing Ding; Xiaoyong Xue; Gang Jin; Yuxin Wu; Yufeng Xie; Yinyin Lin (IEICE Trans. Electron., 2010)

Novel RRAM programming technology for instant-on and high-security FPGAs. - Xiaoyong Xue; Wenxiang Jian; Yufeng Xie; Qing Dong; Rui Yuan; Yinyin Lin (ASICON, 2011)

Novel 2T programmable element to improve density and performance of FPGA. - Xiaoyong Xue; Yufeng Xie; Yinyin Lin (IEICE Electron. Express, 2011)

A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction. - Xiaoyong Xue; W. X. Jian; Jianguo Yang; F. J. Xiao; G. Chen; X. L. Xu; Y. F. Xie; Yinyin Lin; R. Huang; Q. T. Zhou; J. G. Wu (VLSIC, 2012)

64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage. - Yufeng Xie; Wenxiang Jian; Xiaoyong Xue; Gang Jin; Yinyin Lin (IEICE Electron. Express, 2012)

A 2Mb ReRAM with two bits error correction codes circuit for high reliability application. - Jianguo Yang; Ying Meng; Xiaoyong Xue; Ryan Huang; Q. T. Zhou; J. G. Wu; Yinyin Lin (ASICON, 2013)

A 0.13 µm 8 Mb Logic-Based Cux Siy O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction. - Xiaoyong Xue; Wenxiang Jian; Jianguo Yang; Fanjie Xiao; Gang Chen; Shuliu Xu; Yufeng Xie; Yinyin Lin; Ryan Huang; Qingtian Zou; Jingang Wu (IEEE J. Solid State Circuits, 2013)

A low cost and high reliability true random number generator based on resistive random access memory. - Jianguo Yang; Juan Xu; Bo Wang; Xiaoyong Xue; Ryan Huang; Qingtian Zou; Jingang Wu; Yinyin Lin (ASICON, 2015)

Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform. - Kai Yang; Yanqing Zhao; Jianguo Yang; Xiaoyong Xue; Yinyin Lin; Jun-Soo Bae (ASICON, 2015)

3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance. - Yinyin Lin; Rui Yuan; Xiaoyong Xue; B. A. Chen (ISCAS, 2015)

A compact pico-second in-situ sensor using programmable ring oscillators for advanced on chip variation characterization in 28nm HKMG. - Yinyin Lin; Xinyi Hu; Jianguo Yang; Xiaoyong Xue (ISCAS, 2016)

Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression. - Yanqing Zhao; Juan Xu; Jianguo Yang; Xiaoyong Xue; Yinyin Lin; Jaehwang Sim (ISCAS, 2016)

A Distributed Graph Database for the Data Management of IoT Systems. - Kosei Ueta; Xiaoyong Xue; Yukikazu Nakamoto; Sena Murakami (iThings/GreenCom/CPSCom/SmartData, 2016)

A self-adaptive write driver with fast termination of step-up pulse for ReRAM. - Jianguo Yang; Xiaoyong Xue; Juan Xu; Fan Ye 001; Yinyin Lin; Ryan Huang; Qingtian Zou; Jingang Wu (IEICE Electron. Express, 2016)

A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security. - Yufeng Xie; Xiaoyong Xue; Jianguo Yang; Yinyin Lin; Qingtian Zou; Ryan Huang; Jingang Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Low-Power Variation-Tolerant Nonvolatile Lookup Table Design. - Xiaoyong Xue; Jianguo Yang; Yinyin Lin; Ryan Huang; Qingtian Zou; Jingang Wu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations. - Yun Yin; Junlin Gou; Junyi Wang; Yarong Fu; Xiaoyong Xue; Yinyin Lin (ASICON, 2017)

A 1.0-3.0GHz LTE transmitter with CIM enhancement. - Yun Yin; Tong Li; Xiaoyong Xue (ASICON, 2017)

A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application. - Jianguo Yang; Yinyin Lin; Yarong Fu; Xiaoyong Xue; B. A. Chen (ISCAS, 2017)

Distributed graph database as base of smart world things. - Kosei Ueta; Yukikazu Nakamoto; Xiaoyong Xue; Sena Murakami (SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI, 2017)

Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory. - Xiaoyong Xue; Yarong Fu; Yanqing Zhao; Juan Xu; Jianguo Yang; Yufeng Xie; Yinyin Lin; Ryan Huang; Qingtian Zou; Jingang Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F2 and K-means Clustering for Power Reduction. - Keji Zhou; Xiaoyong Xue; Jianguo Yang; Xiaoxin Xu; Hangbing Lv; Mingyu Wang 001; Ming-e Jing; Wenjun Liu; Xiaoyang Zeng; Steve S. Chung; Jing Li; Ming Liu 022 (A-SSCC, 2018)

A Physically Unclonable Function with BER < 0.35% for Secure Chip Authentication Using Write Speed Variation of RRAM. - Jianguo Yang; Xing Li; Tao Wang; Xiaoyong Xue; Zhiliang Hong; Yuanyuan Wang; David Wei Zhang; Hongliang Lu (ESSDERC, 2018)

An Automatic Task Partition Method for Multi-core System. - Ming-e Jing; Yujie Huang; Yibo Fan; Xiaoyong Xue; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2018)

An Orthogonal Algorithm for Key Management in Hardware Obfuscation. - Jiawei Wang; Yuejun Zhang; Pengjun Wang; Zhicun Luan; Xiaoyong Xue; Xiaoyang Zeng; Qiaoyan Yu (AsianHOST, 2019)

Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications. - Yujie Cai; Keji Zhou; Xiaoyong Xue; Mingyu Wang; Xiaoyang Zeng (ASICON, 2019)

A High Reliability 500 µW Resistance-to-Digital Interface Circuit for SnO2 Gas Sensor IoT Applications. - Jianguo Yang; Xiaowen Li; Qingting Ding; Xiaoyong Xue; Xiaoxin Xu; Qing Luo; Hangbing Lv; Ming Liu 022 (ASICON, 2019)

A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key. - Xiaoyong Xue; Jianguo Yang; Yuejun Zhang; Mingyu Wang 001; Hangbing Lv; Xiaoyang Zeng; Ming Liu 022 (A-SSCC, 2019)

A 0.75 V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique. - Jiahao Yin; Chunmeng Dou; Danian Dong; Jie Yu 027; Xiaoxin Xu; Qing Luo; Tiancheng Gong; Lu Tai; Peng Yuan; Xiaoyong Xue; Ming Liu 022; Hangbing Lv (IEICE Electron. Express, 2019)

Directly Obtaining Matching Points without Keypoints for Image Stitching. - Yujie Huang; Ming-e Jing; Yibo Fan; Xiaoyong Xue; Xiaoyang Zeng (ISCAS, 2020)

A Parallel Change Detection Method for Spatiotemporally Multi-Temporal SAR Image Based On Enhance Learning and Wavelet. - Jinxi Peng; Yuanqi Su; Xiaorong Xue; Yi Li; Bin Liu; Xiaoyong Xue; Aihua Wu 009 (ISCID, 2020)

A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm2 using Sneaking Current Suppression and Compensation Techniques. - Jianguo Yang; Xiaoyong Xue; Xiaoxin Xu; Hangbing Lv; Feng Zhang 014; Xiaoyang Zeng; Meng-Fan Chang; Ming Liu 022 (VLSI Circuits, 2020)

A Low Power 4T2C nvSRAM With Dynamic Current Compensation Operation Scheme. - Chao Liu; Jianguo Yang; Pengfei Jiang; Qiao Wang; Donglin Zhang; Tiancheng Gong; Qingting Ding; Yuling Zhao; Qing Luo; Xiaoyong Xue; Hangbing Lv; Ming Liu 022 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Algorithm/Hardware Co-Design Configurable SAR ADC with Low Power for Computing-in-Memory in 28nm CMOS. - Zhiwang Guo; Deyang Chen; Xiaoyong Xue (ASICON, 2021)

Novel 15T SRAM Cell for Low Voltage High Reliability Application. - Yongkang Han; Yulin Zhao; Qiao Hu; Xuanzhi Liu; Bo Peng; Haijun Jiang; Jianguo Yang; Xiaoyong Xue (ASICON, 2021)

Arbitrary Style Transfer via Learning to Paint in the Feature Domain. - Yujie Huang; Yixuan Liu; Ming-e Jing; Mingyu Wang; Xiaoyong Xue; Xiaoyang Zeng; Yibo Fan (ASICON, 2021)

Combining Max Pooling and ReLU Activation Function in Stochastic Computing. - Lixing Li; Deyang Chen; Xiaoyong Xue; Xiaoyang Zeng (ASICON, 2021)

Intra-array Non-Idealities Modeling and Algorithm Optimization for RRAM-based Computing-in-Memory Applications. - Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Zhiwang Guo; Xiaoyong Xue; Xiaoyang Zeng (ASICON, 2021)

Fast Style Transfer with High Shape Retention. - Yujie Huang; Yi Ling; Ming-e Jing; Xiaoyong Xue; Xiaoyang Zeng; Yibo Fan (ISCAS, 2021)

24.2 A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µ m2 Cell Size Using Self-Adaptive Delayed Termination and Multi-Cell Reference. - Jianguo Yang; Xiaoyong Xue; Xiaoxin Xu; Qiao Wang; Haijun Jiang; Jie Yu 027; Danian Dong; Feng Zhang 014; Hangbing Lv; Ming Liu 022 (ISSCC, 2021)

Orthogonal obfuscation based key management for multiple IP protection. - Yuejun Zhang; Jiawei Wang; Pengjun Wang; Xiaoyong Xue; Xiaoyang Zeng (Integr., 2021)

High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications. - Keji Zhou; Xiaoyong Xue; Jianguo Yang; Xiaoxin Xu; Hangbing Lv; Ming-e Jing; Jing Li; Xiaoyang Zeng; Ming Liu 022 (IEEE J. Solid State Circuits, 2021)

An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications. - Keji Zhou; Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Deyang Chen; Yujie Huang; Ming-e Jing; Jun Han 003; Haidong Tian; Xiankui Xiong; Qi Liu 010; Xiaoyong Xue; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

NIMBLE: A Neuromorphic Learning Scheme and Memristor Based Computing-in-Memory Engine for EMG Based Hand Gesture Recognition. - Fengshi Tian; Jingwen Jiang; Jinhao Liang; Zhiyuan Zhang; Jiahe Shi; Chaoming Fang; Hui Wu 010; Xiaoyong Xue; Xiaoyang Zeng (ISCAS, 2022)

HashC: Making DNNs' Coverage Testing Finer and Faster. - Weidi Sun; Xiaoyong Xue; Yuteng Lu; Meng Sun 002 (SETTA, 2022)

A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. - Keji Zhou; Xinru Jia; Chenyang Zhao 008; Xumeng Zhang; Guangjian Wu; Chen Mu; Haozhe Zhu; Yanting Ding; Chixiao Chen; Xiaoyong Xue; Xiaoyang Zeng; Qi Liu 010 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A 28 nm 512 Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for high density and low BER cryptographic key in IoT devices. - Jianguo Yang; Ruijun Lin; Keji Zhou; Yuejun Zhang; Xiaoyong Xue; Hangbing Lv (Microelectron. J., 2022)

A 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications. - Keji Zhou; Ruijun Lin; Zhiwang Guo; Yixuan Liu; Jingwen Jiang; Chenyang Zhao; Jinbei Fang; Xiaoxin Xu; Xiaoyong Xue; Xiaoyang Zeng (Microelectron. J., 2022)

kProp: Multi-neuron Relaxation Method for Neural Network Robustness Verification. - Xiaoyong Xue; Xiyue Zhang 001; Meng Sun 002 (FSEN, 2023)

Branch and Bound for Sigmoid-Like Neural Network Verification. - Xiaoyong Xue; Meng Sun 002 (ICFEM, 2023)

NBSSN: A Neuromorphic Binary Single-Spike Neural Network for Efficient Edge Intelligence. - Ziyang Shen; Fengshi Tian; Jingwen Jiang; Chaoming Fang; Xiaoyong Xue; Jie Yang 033; Mohamad Sawan (ISCAS, 2023)

A 9Mb HZO-Based Embedded FeRAM with 1012-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier. - Jianguo Yang; Qing Luo; Xiaoyong Xue; Haijun Jiang; Qiqiao Wu; Zhongze Han; Yue Cao; Yongkang Han; Chunmeng Dou; Hangbing Lv; Qi Liu 010; Ming Liu 022 (ISSCC, 2023)

MedTiny: Enhanced Mediator Modeling Language for Scalable Parallel Algorithms. - Xiangyu Li; Yihao Zhang; Xiaokun Luan; Xiaoyong Xue; Meng Sun 002 (QRS Companion, 2023)

A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications. - Deyang Chen; Zhiwang Guo; Jinbei Fang; Chenyang Zhao 008; Jingwen Jiang; Keji Zhou; Haidong Tian; Xiankui Xiong; Xiaoyong Xue; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application. - Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Xiaoyong Xue; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance. - Xunming Zhang; Long Liu; Di Wang 042; Ruijun Lin; Heyong Yang; Xiaoxin Xu; Jianguo Yang; Guozhong Xing; Xiaoyong Xue; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices. - Zhiwang Guo; Deyang Chen; Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Yixuan Liu; Haidong Tian; Xiankui Xiong; Keji Zhou; Xiaoyong Xue; Qi Liu 010; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

HashC: Making deep learning coverage testing finer and faster. - Weidi Sun; Xiaoyong Xue; Yuteng Lu; Jia Zhao; Meng Sun 002 (J. Syst. Archit., 2023)

Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications. - Jingwen Jiang; Keji Zhou; Jinhao Liang; Fengshi Tian; Chenyang Zhao 008; Jianguo Yang; Xiaoyong Xue; Xiaoyang Zeng (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications. - Lizhou Wu; Chenyang Zhao 008; Jingbo Wang; Xueru Yu; Shoumian Chen; Chen Li; Jun Han 003; Xiaoyong Xue; Xiaoyang Zeng (ASPDAC, 2024)

Optimal Solution Guided Branching Strategy for Neural Network Branch and Bound Verification. - Xiaoyong Xue; Meng Sun 002 (ICECCS, 2024)

SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure. - Yuanyuan Han; Xu Cheng 002; Xiaoyong Xue; Jun Han 003; Jiawei Xu 001; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 28-nm 36 Kb SRAM CIM Engine With 0.173 μm2 4T1T Cell and Self-Load-0 Weight Update for AI Inference and Training Applications. - Chenyang Zhao 008; Jinbei Fang; Xiaoli Huang; Deyang Chen; Zhiwang Guo; Jingwen Jiang; Jiawei Wang; Jianguo Yang; Jun Han 003; Peng Zhou 021; Xiaoyong Xue; Xiaoyang Zeng (IEEE J. Solid State Circuits, 2024)

A 1024-Spin Scalable Ising Machine With Capacitive Coupling and Progressive Annealing Method for Combination Optimization Problems. - Yixuan Liu; Zhongze Han; Qiqiao Wu; Honghu Yang; Yue Cao; Yongkang Han; Haijun Jiang; Xiaoyong Xue; Jianguo Yang; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A PMOS-Based Deep Cryogenic CMOS Temperature Sensor Achieving a Range from 10K to 410K with a Relative Inaccuracy of 0.5% (3σ). - Xingyu Qi; Yingzhe Sha; Xufeng Kou; Xiaoyong Xue; Peng Wang; Zhangcheng Huang 001; Qi Liu 010; Ming Liu 022 (CICC, 2025)

Garbage collection optimization with data separation for large data storage in deep learning applications. - Qiang Zhou; Sirui Peng; Taoran Shen; Jie Yin; Tieli Sun; Xiaoyong Xue (Microelectron. J., 2025)

Runtime Backdoor Detection for Federated Learning via Representational Dissimilarity Analysis. - Xiyue Zhang 001; Xiaoyong Xue; Xiaoning Du 001; Xiaofei Xie; Yang Liu 003; Meng Sun 002 (IEEE Trans. Dependable Secur. Comput., 2025)

Light-CIM: A Lightweight ADC/DAC-Fewer RRAM CIM DNN Accelerator With Fully Analog Tiles and Nonideality-Aware Algorithm for Consumer Electronics. - Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Xiaoyong Xue; Xiaoyang Zeng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

EF-CIM: An Endurance Friendly CIM Accelerator Using Embedded NVM With Bit-Aware Wear Leveling for Efficient Light-Weight On-Chip Training in Edge Devices. - Zhiwang Guo; Jingwen Jiang; Deyang Chen; Jinbei Fang; Jianguo Yang; Jun Han 003; Xiaoyong Xue; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Enhancing All-to-All RRAM Ising Machines With Randomized Granular Update Strategies for Solving Combinatorial Optimization Problems. - Yixuan Liu; Qiqiao Wu; Honghu Yang; Chengshuo Yu; Keji Zhou; Yu Jiang; Haijun Jiang; Hailan Yi; Xiaoyong Xue; Jianguo Yang; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)