Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network. - Xiaoyu Sun 001; Rui Liu 005; Yi-Ju Chen; Hsiao-Yun Chiu; Wei-Hao Chen; Meng-Fan Chang; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. - Xiaoyu Sun 001; Xiaochen Peng; Pai-Yu Chen; Rui Liu 005; Jae-sun Seo; Shimeng Yu (ASP-DAC, 2018)

Parallelizing SRAM arrays with customized bit-cell for binary neural networks. - Rui Liu 005; Xiaochen Peng; Xiaoyu Sun 001; Win-San Khwa; Xin Si; Jia-Jing Chen; Jia-Fang Li; Meng-Fan Chang; Shimeng Yu (DAC, 2018)

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. - Xiaoyu Sun 001; Shihui Yin; Xiaochen Peng; Rui Liu 005; Jae-sun Seo; Shimeng Yu (DATE, 2018)

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. - Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xin Si; En-Yu Yang; Xiaoyu Sun 001; Rui Liu 005; Pai-Yu Chen; Qiang Li 021; Shimeng Yu; Meng-Fan Chang (ISSCC, 2018)

A Versatile ReRAM-based Accelerator for Convolutional Neural Networks. - Manqing Mao; Xiaoyu Sun 001; Xiaochen Peng; Shimeng Yu; Chaitali Chakrabarti (SiPS, 2018)

A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks. - Shihui Yin; Xiaoyu Sun 001; Shimeng Yu; Jae-sun Seo; Chaitali Chakrabarti (SiPS, 2018)

A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10-6 Native Bit Error Rate. - Yachun Pang; Bin Gao 006; Dong Wu; Shengyu Yi; Qi Liu 010; Wei-Hao Chen; Ting-Wei Chang; Wei-En Lin; Xiaoyu Sun 001; Shimeng Yu; He Qian; Meng-Fan Chang; et al. (ISSCC, 2019)

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. - Xin Si; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; Yen-Cheng Chiu; Wei-Chen Wei; Ssu-Yen Wu; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; et al. (ISSCC, 2019)

Inference engine benchmarking across technological platforms from CMOS to RRAM. - Xiaochen Peng; Minkyu Kim 001; Xiaoyu Sun 001; Shihui Yin; Titash Rakshit; Ryan M. Hatcher; Jorge A. Kittl; Jae-sun Seo; Shimeng Yu (MEMSYS, 2019)

High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS. - Shihui Yin; Xiaoyu Sun 001; Shimeng Yu; Jae-sun Seo (CoRR, 2019)

Impact of Non-Ideal Characteristics of Resistive Synaptic Devices on Implementing Convolutional Neural Networks. - Xiaoyu Sun 001; Shimeng Yu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. - Shihui Yin; Jae-sun Seo; Yulhwa Kim; Xu Han; Hugh J. Barnaby; Shimeng Yu; Yandong Luo; Wangxin He; Xiaoyu Sun 001; Jae-Joon Kim (IEEE Micro, 2019)

A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. - Xin Si; Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Hiroyuki Yamauchi; Qiang Li 021; Meng-Fan Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects. - Shimeng Yu; Xiaoyu Sun 001; Xiaochen Peng; Shanshi Huang (CICC, 2020)

Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories. - Shanshi Huang; Xiaoyu Sun 001; Xiaochen Peng; Hongwu Jiang; Shimeng Yu (DATE, 2020)

The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures. - Xiaoming Chen 003; Kai Ni 004; Michael T. Niemier; Dayane Reis; Xiaoyu Sun 001; Panni Wang; Suman Datta; Xiaobo Sharon Hu; Xunzhao Yin; Matthew Jerry; Shimeng Yu; Ann Franchesca Laguna (IEEE Des. Test, 2020)

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. - Xin Si; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Qiang Li 021; Meng-Fan Chang; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; et al. (IEEE J. Solid State Circuits, 2020)

Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security. - Wantong Li; Shanshi Huang; Xiaoyu Sun 001; Hongwu Jiang; Shimeng Yu (CICC, 2021)

A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References. - Wantong Li; Xiaoyu Sun 001; Hongwu Jiang; Shanshi Huang; Shimeng Yu (ESSDERC, 2021)

Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing. - Wangxin He; Wonbo Shim; Shihui Yin; Xiaoyu Sun 001; Deliang Fan; Shimeng Yu; Jae-sun Seo (IRPS, 2021)

A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source. - Bohan Lin; Yachuan Pang; Bin Gao 006; Jianshi Tang; Dong Wu; Ting-Wei Chang; Wei-En Lin; Xiaoyu Sun 001; Shimeng Yu; Meng-Fan Chang; He Qian; Huaqiang Wu (IEEE J. Solid State Circuits, 2021)

Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM. - Gauthaman Murali; Xiaoyu Sun 001; Shimeng Yu; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Compute-in-Memory with Emerging non-Volatile Memories for Accelerating Deep Neural Networks. - Xiaoyu Sun 001 (2021)

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References. - Wantong Li; Xiaoyu Sun 001; Shanshi Huang; Hongwu Jiang; Shimeng Yu (IEEE J. Solid State Circuits, 2022)

Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices. - Shanshi Huang; Xiaoyu Sun 001; Xiaochen Peng; Hongwu Jiang; Shimeng Yu (ACM Trans. Design Autom. Electr. Syst., 2022)

Non-volatile Memory Technologies for Edge AI Applications. - Xiaoyu Sun 001; Win-San Khwa; Xiaochen Peng; Meng-Fan Chang; Kerem Akarvardar (ICCAD, 2024)

Neural Architecture Search of Hybrid Models for NPU-CIM Heterogeneous AR/VR Devices. - Yiwei Zhao; Ziyun Li; Win-San Khwa; Xiaoyu Sun 001; Sai Qian Zhang; Syed Shakib Sarwar; Kleber Hugo Stangherlin; Yi-Lun Lu; Jorge Tomás Gómez; Jae-Sun Seo; Phillip B. Gibbons; Barbara De Salvo; et al. (CoRR, 2024)

Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework. - Xiaoyu Sun 001; Xiaochen Peng; Sai Qian Zhang; Jorge Gomez 002; Win-San Khwa; Syed Shakib Sarwar; Ziyun Li; Weidong Cao 001; Zhao Wang; Chiao Liu; Meng-Fan Chang; Barbara De Salvo; et al. (ACM Trans. Design Autom. Electr. Syst., 2024)

Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. - Xiaoyu Sun 001; Weidong Cao 001; Brian Crafton; Kerem Akarvardar; Haruki Mori; Hidehiro Fujiwara; Hiroki Noguchi; Yu-Der Chih; Meng-Fan Chang; Yih Wang; Tsung-Yung Jonathan Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)