FeMAT: Exploring In-Memory Processing in Multifunctional FeFET-Based Memory Array. - Xiaoyu Zhang 009; Xiaoming Chen 003; Yinhe Han 001 (ICCD, 2019)

BRAHMS: Beyond Conventional RRAM-based Neural Network Accelerators Using Hybrid Analog Memory System. - Tao Song; Xiaoming Chen 003; Xiaoyu Zhang 009; Yinhe Han 001 (DAC, 2021)

FeMIC: Multi-Operands in-Memory Computing Based on FeFETs. - Rui Liu; Xiaoyu Zhang 009; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (ASP-DAC, 2022)

Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory Architecture. - Xiaoyu Zhang 009; Rui Liu; Tao Song; Yuxin Yang 002; Yinhe Han 001; Xiaoming Chen 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

FSPA: An FeFET-based Sparse Matrix-Dense Vector Multiplication Accelerator. - Xiaoyu Zhang 009; Zerun Li; Rui Liu; Xiaoming Chen 003; Yinhe Han 001 (DAC, 2023)

Meltrix: A RRAM-Based Polymorphic Architecture Enhanced by Function Synthesis. - Boyu Long; Libo Shen; Xiaoyu Zhang 009; Yinhe Han 001; Xian-He Sun; Xiaoming Chen 003 (ICCAD, 2023)

LIM-GEN: A Data-Guided Framework for Automated Generation of Heterogeneous Logic-in-Memory Architecture. - Libo Shen; Boyu Long; Rui Liu; Xiaoyu Zhang 009; Yinhe Han 001; Xiaoming Chen 003 (ICCAD, 2023)

Hardware-Software Co-Design for Content-Based Sparse Attention. - Rui Tang; Xiaoyu Zhang 009; Rui Liu; Zhejian Luo; Xiaoming Chen 003; Yinhe Han 001 (ICCD, 2023)

FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing. - Rui Liu; Xiaoyu Zhang 009; Zhiwen Xie; Xinyu Wang; Zerun Li; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

MemSort: In-Memory Sorting Architecture. - Rui Liu; Xiaoyu Zhang 009; Xinyu Wang; Feng Min; Zhejian Luo; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (ICCD, 2024)

GAS: General-Purpose In-Memory-Computing Accelerator for Sparse Matrix Multiplication. - Xiaoyu Zhang 009; Zerun Li; Rui Liu; Xiaoming Chen 003; Yinhe Han 001 (IEEE Trans. Computers, 2024)

Crypto-DSEDA: A Domain-Specific EDA Flow for CiM-Based Cryptographic Accelerators. - Rui Liu; Zerun Li; Xiaoyu Zhang 009; Wanqian Li; Libo Shen; Rui Tang; Zhejian Luo; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (IEEE Des. Test, 2024)

In-Memory Computing Accelerator for Iterative Linear Algebra Solvers. - Rui Liu; Zerun Li; Xiaoyu Zhang 009; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (IEEE Comput. Archit. Lett., 2025)

A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing. - Zerun Li; Xiaoming Chen 003; Yuxin Yang 002; Feng Min; Xiaoyu Zhang 009; Yinhe Han 001 (IEEE Trans. Computers, 2025)