An Enhanced Design Methodology for Resonant Clock Trees. - Somayyeh Rahimian; Vasilis F. Pavlidis; Xifan Tang; Giovanni De Micheli (J. Low Power Electron., 2013)

Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise. - Hu Xu 002; Vasilis F. Pavlidis; Xifan Tang; Wayne P. Burleson; Giovanni De Micheli (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Pattern-based FPGA logic block and clustering algorithm. - Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (FPL, 2014)

A high-performance low-power near-Vt RRAM-based FPGA. - Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (FPT, 2014)

TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs. - Xifan Tang; Jian Zhang 067; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ISCAS, 2014)

Novel configurable logic block architecture exploiting controllable-polarity transistors. - Pierre-Emmanuel Gaillardon; Xifan Tang; Giovanni De Micheli (ReCoSoC, 2014)

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs. - Jian Zhang 067; Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A ultra-low-power FPGA based on monolithically integrated RRAMs. - Pierre-Emmanuel Gaillardon; Xifan Tang; Jury Sandrini; Maxime Thammasack; Somayyeh Rahimian Omam; Davide Sacchetto; Yusuf Leblebici; Giovanni De Micheli (DATE, 2015)

Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only). - Pierre-Emmanuel Gaillardon; Gain Kim; Xifan Tang; Luca Gaetano Amarù; Giovanni De Micheli (FPGA, 2015)

Accurate power analysis for near-Vt RRAM-based FPGA. - Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (FPL, 2015)

FPGA-SPICE: A simulation-based power estimation framework for FPGAs. - Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ICCD, 2015)

A study on buffer distribution for RRAM-based FPGA routing structures. - Somayyeh Rahimian Omam; Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (LASCAS, 2015)

A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells. - Pierre-Emmanuel Gaillardon; Xifan Tang; Gain Kim; Giovanni De Micheli (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only). - Xifan Tang; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (FPGA, 2016)

A Study on the Programming Structures for RRAM-Based FPGA Architectures. - Xifan Tang; Gain Kim; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. - Zhufei Chu; Xifan Tang; Mathias Soeken; Ana Petkovska; Grace Zgheib; Luca Gaetano Amarù; Yinshui Xia; Paolo Ienne; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (ACM Great Lakes Symposium on VLSI, 2017)

Physical Design Considerations of One-level RRAM-based Routing Multiplexers. - Xifan Tang; Edouard Giacomin; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (ISPD, 2017)

Optimization opportunities in RRAM-based FPGA architectures. - Xifan Tang; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (LASCAS, 2017)

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure. - Xifan Tang; Edouard Giacomin; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers. - Xifan Tang; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (IEEE Trans. Emerg. Top. Comput., 2017)

Circuit Design, Architecture and CAD for RRAM-based FPGAs. - Xifan Tang (2017)

Post-P&R Performance and Power Analysis for RRAM-Based FPGAs. - Xifan Tang; Edouard Giacomin; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs. - Xifan Tang; Edouard Giacomin; Aurélien Alacchi; Baudouin Chauviere; Pierre-Emmanuel Gaillardon (FPL, 2019)

LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper. - Walter Lau Neto; Max Austin; Scott Temple; Luca G. Amarù; Xifan Tang; Pierre-Emmanuel Gaillardon (ICCAD, 2019)

A Study on Switch Block Patterns for Tileable FPGA Routing Architectures. - Xifan Tang; Edouard Giacomin; Aurélien Alacchi; Pierre-Emmanuel Gaillardon (FPT, 2019)

Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs. - Walter Lau Neto; Xifan Tang; Max Austin; Luca G. Amarù; Pierre-Emmanuel Gaillardon (ISVLSI, 2019)

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories. - João Vieira; Edouard Giacomin; Yasir Mahmood Qureshi; Marina Zapater; Xifan Tang; Shahar Kvatinsky; David Atienza; Pierre-Emmanuel Gaillardon (VLSI-SoC, 2019)

Accelerating Inference on Binary Neural Networks with Digital RRAM Processing. - João Vieira; Edouard Giacomin; Yasir Mahmood Qureshi; Marina Zapater; Xifan Tang; Shahar Kvatinsky; David Atienza; Pierre-Emmanuel Gaillardon (VLSI-SoC (Selected Papers), 2019)

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs. - Xifan Tang; Edouard Giacomin; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Scalable Mixed Synthesis Framework for Heterogeneous Networks. - Max Austin; Scott Temple; Walter Lau Neto; Luca G. Amarù; Xifan Tang; Pierre-Emmanuel Gaillardon (DATE, 2020)

A RRAM-based FPGA for Energy-efficient Edge Computing. - Xifan Tang; Edouard Giacomin; Patsy Cadareanu; Ganesh Gore; Pierre-Emmanuel Gaillardon (DATE, 2020)

OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs. - Xifan Tang; Edouard Giacomin; Baudouin Chauviere; Aurélien Alacchi; Pierre-Emmanuel Gaillardon (IEEE Micro, 2020)

Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis. - Scott Temple; Walter Lau Neto; Ashton Snelgrove; Xifan Tang; Pierre-Emmanuel Gaillardon (DAC, 2021)

Taping out an FPGA in 24 hours with OpenFPGA: The SOFA Project. - Xifan Tang; Ganesh Gore; Grant Brown; Pierre-Emmanuel Gaillardon (FPL, 2021)

Exploring eFPGA-based Redaction for IP Protection. - Jitendra Bhandari; Abdul Khader Thalakkattu Moosa; Benjamin Tan 001; Christian Pilato; Ganesh Gore; Xifan Tang; Scott Temple; Pierre-Emmanuel Gaillardon; Ramesh Karri (ICCAD, 2021)

Smart-Redundancy: An Alternative SEU/SET Mitigation Method for FPGAs. - Aurélien Alacchi; Edouard Giacomin; Xifan Tang; Pierre-Emmanuel Gaillardon (ISCAS, 2021)

A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs. - Ganesh Gore; Xifan Tang; Pierre-Emmanuel Gaillardon (ISPD, 2021)

ALICE: an automatic design flow for eFPGA redaction. - Chiara Muscari Tomajoli; Luca Collini; Jitendra Bhandari; Abdul Khader Thalakkattu Moosa; Benjamin Tan 001; Xifan Tang; Pierre-Emmanuel Gaillardon; Ramesh Karri; Christian Pilato (DAC, 2022)

Architectural Exploration of Heterogeneous FPGAs for Performance Enhancement of ML Benchmarks. - Anubhav Mishra; Nanditha Rao; Ganesh Gore; Xifan Tang (APCCAS, 2023)

A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design. - Ganesh Gore; Xifan Tang; Pierre-Emmanuel Gaillardon (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction. - Jitendra Bhandari; Abdul Khader Thalakkattu Moosa; Benjamin Tan 001; Christian Pilato; Ganesh Gore; Xifan Tang; Scott Temple; Pierre-Emmanuel Gaillardon; Ramesh Karri (IEEE Trans. Very Large Scale Integr. Syst., 2023)

FPGA EDA - Design Principles and Implementation - Kaihui Tu; Xifan Tang; Cunxi Yu; Lana Josipovic; Zhufei Chu (Springer, 2024)

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction. - Luca Collini; Jitendra Bhandari; Chiara Muscari Tomajoli; Abdul Khader Thalakkattu Moosa; Benjamin Tan 001; Xifan Tang; Pierre-Emmanuel Gaillardon; Ramesh Karri; Christian Pilato (CoRR, 2025)

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction. - Luca Collini; Jitendra Bhandari; Chiara Muscari Tomajoli; Abdul Moosa; Benjamin Tan 001; Xifan Tang; Pierre-Emmanuel Gaillardon; Ramesh Karri; Christian Pilato (ACM Trans. Design Autom. Electr. Syst., 2025)