On finding undetectable and redundant faults in synchronous sequential circuits. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (ICCD, 1998)

MIX: A Test Generation System for Synchronous Sequential Circuits. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1998)

On Removing Redundant Faults in Synchronous Sequential Circuits. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (VTS, 1998)

Full Scan Fault Coverage With Partial Scan. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (DATE, 1999)

Techniques for improving the efficiency of sequential circuit test generation. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1999)

Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. - Sudhakar M. Reddy; Irith Pomeranz; Nadir Z. Basturkmen; Xijiang Lin (VTS, 1999)

SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. - Xijiang Lin; Wu-Tung Cheng; Irith Pomeranz; Sudhakar M. Reddy (VTS, 2000)

Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. - Irith Pomeranz; Sudhakar M. Reddy; Xijiang Lin (Asian Test Symposium, 2001)

On static test compaction and test pattern ordering for scan designs. - Xijiang Lin; Janusz Rajski; Irith Pomeranz; Sudhakar M. Reddy (ITC, 2001)

Conflict driven techniques for improving deterministic test pattern generation. - Chen Wang 014; Sudhakar M. Reddy; Irith Pomeranz; Xijiang Lin; Janusz Rajski (ICCAD, 2002)

Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. - Nandu Tendolkar; Rajesh Raina; Rick Woltenberg; Xijiang Lin; Bruce Swanson; Greg Aldrich (VTS, 2002)

Test generation for designs with multiple clocks. - Xijiang Lin; Rob Thompson (DAC, 2003)

High-Frequency, At-Speed Scan Testing. - Xijiang Lin; Ron Press; Janusz Rajski; Paul Reuter; Thomas Rinderknecht; Bruce Swanson; Nagesh Tamarapalli (IEEE Des. Test Comput., 2003)

Propagation delay fault: a new fault model to test delay faults. - Xijiang Lin; Janusz Rajski (ASP-DAC, 2005)

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. - Matthias Beck; Olivier Barondeau; Martin Kaibel; Frank Poehl; Xijiang Lin; Ron Press (DATE, 2005)

Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study. - Matthias Beck; Olivier Barondeau; Frank Poehl; Xijiang Lin; Ron Press (VTS, 2005)

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. - Xijiang Lin; Kun-Han Tsai; Chen Wang 014; Mark Kassab; Janusz Rajski; Takeo Kobayashi; Randy Klingenberg; Yasuo Sato; Shuji Hamada; Takashi Aikyo (ATS, 2006)

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. - Santiago Remersaro; Xijiang Lin; Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (ITC, 2006)

The Impacts of Untestable Defects on Transition Fault Testing. - Xijiang Lin; Janusz Rajski (VTS, 2006)

Scan Tests with Multiple Fault Activation Cycles for Delay Faults. - Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz; Xijiang Lin; Janusz Rajski (VTS, 2006)

Programmable Logic BIST for At-speed Test. - Yu Huang 005; Xijiang Lin (ATS, 2007)

Test Generation for Timing-Critical Transition Faults. - Xijiang Lin; Mark Kassab; Janusz Rajski (ATS, 2007)

Low Shift and Capture Power Scan Tests. - Santiago Remersaro; Xijiang Lin; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (VLSI Design, 2007)

Scan-Based Tests with Low Switching Activity. - Santiago Remersaro; Xijiang Lin; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (IEEE Des. Test Comput., 2007)

Test Power Reduction by Blocking Scan Cell Outputs. - Xijiang Lin; Janusz Rajski (ATS, 2008)

Low Power Scan Shift and Capture in the EDT Environment. - Dariusz Czysz; Mark Kassab; Xijiang Lin; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (ITC, 2008)

Test Generation for Interconnect Opens. - Xijiang Lin; Janusz Rajski (ITC, 2008)

Reducing Scan Shift Power at RTL. - Elif Alpaslan; Yu Huang 005; Xijiang Lin; Wu-Tung Cheng; Jennifer Dworak (VTS, 2008)

Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells. - Xijiang Lin; Yu Huang 005 (J. Electron. Test., 2008)

Test Generation for Designs with On-Chip Clock Generators. - Xijiang Lin; Mark Kassab (Asian Test Symposium, 2009)

Low-Power Scan Operation in Test Compression Environment. - Dariusz Czysz; Mark Kassab; Xijiang Lin; Grzegorz Mrugalski; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Adaptive Low Shift Power Test Pattern Generator for Logic BIST. - Xijiang Lin; Janusz Rajski (Asian Test Symposium, 2010)

Low capture power at-speed test in EDT environment. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Xijiang Lin; Nilanjan Mukherjee 001; Mark Kassab (ITC, 2010)

Detecting and diagnosing open defects. - Dat Tran; LeRoy Winemberg; Darrell Carder; Xijiang Lin; Joe LeBritton; Bruce Swanson (ITC, 2010)

Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. - Tom Waayers; Richard Morren; Xijiang Lin; Mark Kassab (ITC, 2010)

On Reducing Scan Shift Activity at RTL. - Elif Alpaslan; Yu Huang 005; Xijiang Lin; Wu-Tung Cheng; Jennifer Dworak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Power Aware Embedded Test. - Xijiang Lin; Elham K. Moghaddam; Nilanjan Mukherjee 001; Benoit Nadeau-Dostie; Janusz Rajski; Jerzy Tyszer (Asian Test Symposium, 2011)

Low power testing - What can commercial DFT tools provide? - Xijiang Lin (IGCC, 2011)

Power Supply Droop and Its Impacts on Structural At-Speed Testing. - Xijiang Lin (Asian Test Symposium, 2012)

On Utilizing Test Cube Properties to Reduce Test Data Volume Further. - Xijiang Lin; Janusz Rajski (Asian Test Symposium, 2012)

Multicycle-aware At-speed Test Methodology. - Kun-Han Tsai; Xijiang Lin (Asian Test Symposium, 2013)

Test compaction for small-delay defects using an effective path selection scheme. - Dong Xiang; Jianbo Li; Krishnendu Chakrabarty; Xijiang Lin (ACM Trans. Design Autom. Electr. Syst., 2013)

Timing-Aware ATPG. - Mark Kassab; Benoit Nadeau-Dostie; Xijiang Lin (Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2014)

Using dynamic shift to reduce test data volume in high-compression designs. - Xijiang Lin; Mark Kassab; Janusz Rajski (ETS, 2014)

On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. - Xijiang Lin; Wu-Tung Cheng; Janusz Rajski (ATS, 2015)

On generating high quality tests based on cell functions. - Xijiang Lin; Sudhakar M. Reddy (ITC, 2015)

Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. - Xijiang Lin; Sudhakar M. Reddy; Janusz Rajski (VLSID, 2015)

On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection. - Xijiang Lin; Sudhakar M. Reddy; Wu-Tung Cheng (ATS, 2016)

Transistor stuck-on fault detection tests for digital CMOS circuits. - Xijiang Lin; Sudhakar M. Reddy; Janusz Rajski (ETS, 2016)

Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill. - Dong Xiang; Kele Shen; Bhargab B. Bhattacharya; Xiaoqing Wen; Xijiang Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Functional Broadside Test Generation Using a Commercial ATPG Tool. - Naixing Wang; Bo Yao 002; Xijiang Lin; Irith Pomeranz (ISVLSI, 2017)

On applying scan based structural test for designs with dual-edge triggered flip-flops. - Xijiang Lin (ITC, 2017)

TEA: A Test Generation Algorithm for Designs with Timing Exceptions. - Naixing Wang; Chen Wang 014; Kun-Han Tsai; Wu-Tung Cheng; Xijiang Lin; Mark Kassab; Irith Pomeranz (ATS, 2019)

On Generating Fault Diagnosis Patterns for Designs with X Sources. - Xijiang Lin; Sudhakar M. Reddy (ETS, 2019)

Test Challenges of Intel IA Cores. - Uri Shpiro; Khen Wee; Kun-Han Tsai; Justyna Zawada; Xijiang Lin (ITC, 2020)

On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation. - Xijiang Lin; Wu-Tung Cheng; Takeo Kobayashi; Andreas Glowatz (ATS, 2021)

Timing Critical Path Validation for Intel ATOM Cores Using Structural Test. - Wei Li; Shih-Yu Yang; Khen Wee; Ricardo Sanchez; Jay Desai; Kun-Han Tsai; Xijiang Lin (VTS, 2021)

Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults. - Irith Pomeranz; Xijiang Lin (IEEE Trans. Very Large Scale Integr. Syst., 2021)

AI Driven Testing. - Yu Huang; Alex Yu; Louis Liu; Xijiang Lin (ITC-Asia, 2024)

DFT for Complex Designs and Test Data Management. - Wu Yang; Jinshan Yu; Pearl He; Xijiang Lin (ITC-Asia, 2024)