SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device. - Xilong Kang; Qingwen Wei; Ningyuan Li 004; Xingyu Xu 008; Hao Cai 001; Bo Liu 019 (ASP-DAC, 2025)

A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs. - Bo Liu 019; Xingyu Xu 008; Yang Zhang 132; Xilong Kang; Qingwen Wei; Zihan Zou; Jun Yang 006; Hao Cai 001; Xin Si (CICC, 2025)

A Layer-wise N: M Sparsity Aware Transformer Accelerator leveraging Temporal Locality with Butterfly Network. - Qinfan Wang; Yuan Song; Xilong Kang; Qingwen Wei; Cai Hao; Bo Liu (ISCAS, 2025)

KV-Cache Oriented Query-Aware Sparse Attention Accelerator With Cross-Stage Precision-Configurable Digital CIM. - Yang Zhang 132; Xilong Kang; Weixuan Wang; Yizhi Ding; Lizheng Ren; Yiran Zhang; Ruiqi Tan; Zhen Wang 019; Hao Cai 001; Bo Liu 019 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)