A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop. - Xin Chen 039; Jun Yang 006; Longxing Shi (IEICE Trans. Electron., 2008)

Analysis of Jitter in CMOS Ring Oscillators due to Power Supply Noise. - Xiaoying Deng; Xin Chen 039; Jun Yang 006; Jianhui Wu (IEICE Trans. Electron., 2009)

A Harmonic-Free All Digital Delay-Locked Loop Using an Improved Fast-Locking Successive Approximation Register-Controlled Scheme. - Kai Huang; Zhikuang Cai; Xin Chen 039; Longxing Shi (IEICE Trans. Electron., 2009)

Dynamic Voltage Scaling for Real-Time Systems with System Workload Analysis. - Zhe Zhang; Xin Chen 039; De-jun Qian; Chen Hu (IEICE Trans. Electron., 2010)

A Novel Combined Proportional-Derivative Control for Electrostatic MEMS Mirror Actuation. - Weiwei Shan; Xin Chen 039 (IEICE Trans. Electron., 2011)

A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique. - Xin Chen 039; Jun Yang 006; Longxing Shi (IEEE Trans. Very Large Scale Integr. Syst., 2011)

BIST design of power switch. - Xin Chen 039; Ning Wu; Wei Hu; Weiwei Shan (IEICE Electron. Express, 2013)

A Design Methodology for Three-Dimensional Hybrid NoC-Bus Architecture. - Lei Zhou 006; Ning Wu; Xin Chen 039 (IEICE Trans. Electron., 2013)

Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware. - Weiwei Shan; Xin Chen 039; Bo Li 033; Peng Cao 002; Jie Li; Gugang Gao; Longxing Shi (IEEE Trans. Instrum. Meas., 2013)

A New Redundant Binary Partial Product Generator for Fast 2n-Bit Multiplier Design. - Xiao-Ping Cui; Wei Hu; Xin Chen 039; Shumin Wang (CSE, 2014)

An optimized delay-aware common subexpression elimination algorithm for hardware implementation of binary-field linear transform. - Xiaoqiang Zhang 001; Ning Wu; Fang Zhou 001; Xin Chen 039 (IEICE Electron. Express, 2014)

Built-in self test design of power switch with clock-gated charge/discharge transistor. - Xin Chen 039; Ning Wu; Na Bai; Hui Huang; Wei Hu (IET Comput. Digit. Tech., 2014)

A scalable multi-pipeline JPEG encoding architecture. - Shichao Yu; Zhizhong Hu; Xin Chen 039 (ICM, 2016)

A Modified Partial Product Generator for Redundant Binary Multipliers. - Xiao-Ping Cui; Weiqiang Liu 001; Xin Chen 039; Earl E. Swartzlander Jr.; Fabrizio Lombardi (IEEE Trans. Computers, 2016)

FPGA based highly efficient MISTY1 architecture. - Yasir Khizar; Ning Wu; Xin Chen 039; Muhammad Rehan Yahya; Xiaoqiang Zhang 001 (IEICE Electron. Express, 2017)

VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors. - Hao Xiao; Xiang Yin 005; Ning Wu; Xin Chen 039; Jun Li 046; Xiaoxing Chen (IET Comput. Digit. Tech., 2018)

Small Area High Speed Configurable FFT Processor. - Xiaoyu Zhang; Xin Chen 039; Ying Zhang 068 (ICICDT, 2019)

A New Hardware Trojan Design: Distinguishing Between Trigger Inputs and Functional Inputs Is Difficult: Work-in-Progress. - Minghui Ge; Ying Zhang 068; Sen Li; Jiaqi Yao; Zhiming Mao; Xin Chen 039 (CODES+ISSS, 2020)

Hardware Trojans Detection Through RTL Features Extraction and Machine Learning. - Jizhong Yang; Ying Zhang 068; Yifeng Hua; Jiaqi Yao; Zhiming Mao; Xin Chen 039 (AsianHOST, 2021)

Efficient Anti-Glare Ceramic Decals Defect Detection by Incorporating Homomorphic Filtering. - Xin Chen 039; Ying Zhang 068; Lang Lin; Junxiang Wang; Jiangqun Ni (Comput. Syst. Sci. Eng., 2021)

Z-domain modeling methodology for homodyne digital optical phase-locked loop. - Xin Chen 039; Xiaoyu Liu; Ying Zhang 068; Yongxin Shan; Qiang Hu; Jun Li 046; Shiqi Lan (IEICE Electron. Express, 2021)

PUF-based Secure Test Wrapper Design for Network-on-Chip. - Ying Zhang 068; Yuanxiang Li; Xin Chen 039; Jizhong Yang; Yifeng Hua; Jiaoyan Yao (HOST, 2022)

Blinding HT: Hiding Hardware Trojan signals traced across multiple sequential levels. - Ying Zhang 068; Minghui Ge; Xin Chen 039; Jiaqi Yao; Zhiming Mao (IET Circuits Devices Syst., 2022)

Hybrid multi-level hardware Trojan detection platform for gate-level netlists based on XGBoost. - Ying Zhang 068; Sen Li; Xin Chen 039; Jiaqi Yao; Zhiming Mao; Jizhong Yang; Yifeng Hua (IET Comput. Digit. Tech., 2022)

FPGA-Based Cross-Hardware MBU Emulation Platform for Layout-Level Digital VLSI. - Xin Chen 039; Liangzhou Huo; Yudong Xie; Zhihao Shen; Zhiqiang Xiang; Changhao Gao; Ying Zhang 068 (ATS, 2023)

Spotlight: An Impairing Packet Transmission Attack Targeting Specific Node in NoC-based TCMP. - Jiaoyan Yao; Ying Zhang 068; Yifeng Hua; Yuanxiang Li; Jizhong Yang; Xin Chen 039 (ETS, 2023)

Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS. - Xin Chen 039; Yuxin Bai; Jianpeng Cao; Lei Wang 226; Xinjie Zhou; Ying Zhang 068; Weiqiang Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

FPGA Design of Blind Zone-Suppressed Phase Frequency Detector via Reset Mask and Edge Recovery Operations. - Xin Chen 039; Yuxin Bai; Xiaoyu Liu; Ying Zhang 068 (Circuits Syst. Signal Process., 2023)

Trade-off Mechanism Between Reliability and Performance for Data-flow Soft Error Detection. - Zhenyu Zhao; Xin Chen 039; Yufan Lu (J. Electron. Test., 2023)

Double-Node-Upset Self-Recoverable Latch Design for Wide Voltage Range Application. - Yuxin Bai; Xin Chen 039; Xinjie Zhou; Yanan Yin; Ying Zhang 068 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application. - Xin Chen 039; Yuxin Bai; Hao Cai 001; Congyi Zhu; Xinjie Zhou; Ying Zhang 068; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

FPGA-Based Implementation and Quantization of Convolutional Neural Networks. - Haozhen Jia; Xin Chen 039; Daxing Dong (CNML, 2025)