Xin Fan

Orcid: 0000-0001-6954-5074

Affiliations:
  • RTWH Aachen University, Aachen, Germany


According to our database1, Xin Fan authored at least 9 papers between 2017 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Discrete Steps towards Approximate Computing.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

2021
Plesiochronous Spread Spectrum Clocking With Guaranteed QoS for In-Band Switching Noise Reduction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
Approximation of Transcendental Functions With Guaranteed Algorithmic QoS by Multilayer Pareto Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2020

2019
Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Physical modeling of bitcell stability in subthreshold SRAMs for leakage-area optimization under PVT variations.
Proceedings of the International Conference on Computer-Aided Design, 2018

A Cortex-M3 Based MCV Featuring AVS with 34nW Static Power, 15.3pJ/inst. Active Energy, and 16% Power Variation Across Process and Temperature.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Towards SRAM leakage power minimization by aggressive standby voltage scaling - Experiments on 40nm test chips.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017


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