Xin Fan

Orcid: 0000-0001-5512-6362

Affiliations:
  • IHP, Frankfurt, Germany


According to our database1, Xin Fan authored at least 19 papers between 2009 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2021
Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2017
Asynchronous and GALS Design -Overview and Perspectives.
Proceedings of the New Generation of CAS, 2017

2016
Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

An Early Stage Design Flow for Switching Noise Attenuation.
J. Circuits Syst. Comput., 2016

2015
Frequency-domain modeling of ground bounce and substrate noise for synchronous and GALS systems.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

A Design Preconditioning Flow for Low-Noise Circuits.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
GALS design of ECC against side-channel attacks - A comparative study.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

2013
GALS Design for Spectral Peak Attenuation of Switching Current.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2012
Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience.
Int. J. Embed. Real Time Commun. Syst., 2012

Asynchronous circuit design: From basics to practical applications.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Exploring pausible clocking based GALS design for 40-nm system integration.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Performance Analysis of GALS Datalink Based on Pausible Clocking.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011
Moonrake chip - GALS demonstrator in 40 nm CMOS technology.
Proceedings of the 2011 International Symposium on System on Chip, 2011

GALS Design for On-chip Ground Bounce Suppression.
Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011

2010
Reducing Electromagnetic Interference Using Globally Asynchronous Locally Synchronous Approach.
J. Low Power Electron., 2010

A GALS FFT processor with clock modulation for low-EMI applications.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
GALS for Bursty Data Transfer based on Clock Coupling.
Proceedings of the 4th International Workshop on the Application of Formal Methods for Globally Asynchronous and Locally Synchronous Design, 2009

Modeling and Reducing EMI in GALS and Synchronous Systems.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Analysis and optimization of pausible clocking based GALS design.
Proceedings of the 27th International Conference on Computer Design, 2009


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