Analysis and optimization of pausible clocking based GALS design. - Xin Fan 003; Milos Krstic; Eckhard Grass (ICCD, 2009)

Modeling and Reducing EMI in GALS and Synchronous Systems. - Tomasz Król; Milos Krstic; Xin Fan 003; Eckhard Grass (PATMOS, 2009)

GALS for Bursty Data Transfer based on Clock Coupling. - Milos Krstic; Xin Fan 003; Eckhard Grass; Frank K. Gürkaynak (FMGALS@DATE, 2009)

A GALS FFT processor with clock modulation for low-EMI applications. - Xin Fan 003; Milos Krstic; Christoph Wolf; Eckhard Grass (ASAP, 2010)

Reducing Electromagnetic Interference Using Globally Asynchronous Locally Synchronous Approach. - Milos Krstic; Tomasz Król; Xin Fan 003; Eckhard Grass (J. Low Power Electron., 2010)

GALS Design for On-chip Ground Bounce Suppression. - Xin Fan 003; Milos Krstic; Christoph Wolf; Eckhard Grass (ASYNC, 2011)

Moonrake chip - GALS demonstrator in 40 nm CMOS technology. - Milos Krstic; Xin Fan 003; Eckhard Grass; Christoph Heer; Birgit Sanders; Luca Benini; Mohammad Reza Kakoee; Alessandro Strano; Davide Bertozzi (SoC, 2011)

Performance Analysis of GALS Datalink Based on Pausible Clocking. - Xin Fan 003; Milos Krstic; Eckhard Grass (ASYNC, 2012)

Exploring pausible clocking based GALS design for 40-nm system integration. - Xin Fan 003; Milos Krstic; Eckhard Grass; Birgit Sanders; Christoph Heer (DATE, 2012)

Asynchronous circuit design: From basics to practical applications. - Eckhard Grass; Milos Krstic; Xin Fan 003; Steffen Zeidler 001 (DDECS, 2012)

Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience. - Milos Krstic; Xin Fan 003; Eckhard Grass; Luca Benini; Mohammad Reza Kakoee; Christoph Heer; Birgit Sanders; Alessandro Strano; Davide Bertozzi (Int. J. Embed. Real Time Commun. Syst., 2012)

GALS Design for Spectral Peak Attenuation of Switching Current. - Xin Fan 003; Oliver Schrape; Miroslav Marinkovic; Peter Dahnert; Milos Krstic; Eckhard Grass (ASYNC, 2013)

GALS design of ECC against side-channel attacks - A comparative study. - Xin Fan 003; Steffen Peter; Milos Krstic (PATMOS, 2014)

A Design Preconditioning Flow for Low-Noise Circuits. - Steffen Zeidler 001; Xin Fan 003; Oliver Schrape; Milos Krstic (DDECS, 2015)

Frequency-domain modeling of ground bounce and substrate noise for synchronous and GALS systems. - Milan Babic; Xin Fan 003; Milos Krstic (PATMOS, 2015)

An Early Stage Design Flow for Switching Noise Attenuation. - Steffen Zeidler 001; Xin Fan 003; Oliver Schrape; Milos Krstic (J. Circuits Syst. Comput., 2016)

Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling. - Xin Fan 003; Mikkel B. Stegmann; Oliver Schrape; Steffen Zeidler 001; Isac G. Jensen; Jannich Thorsen; Tobias Bjerregaard; Milos Krstic (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Asynchronous and GALS Design -Overview and Perspectives. - Milos Krstic; Eckhard Grass; Xin Fan 003 (NGCAS, 2017)

Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment. - Jianan Wen; Markus Ulbricht 002; Eduardo Pérez; Xin Fan 003; Milos Krstic (DDECS, 2021)