A digital-mixing-based method for timing skew estimation in time-interleaved ADCs. - Xin Li 099; Desheng Ding; Chenggang Yan 002; Jianhui Wu 001 (Microelectron. J., 2019)

Active Noise Shaping SAR ADC Based on ISDM with the 5MHz Bandwidth. - Bo Gao; Xin Li 099; Chenggang Yan 002; Jianhui Wu 001 (ISCAS, 2020)

A Review on Calibration Methods of Timing-Skew in Time-Interleaved ADCs. - Xin Li 099; Cheng Huang 005; Desheng Ding; Jianhui Wu 001 (J. Circuits Syst. Comput., 2020)

A Low-Spur MASH Delta-Sigma Modulator With an Adaptive Length Extension Technique. - Xin Ding 003; Chenggang Yan 002; Xin Li 099; Jianhui Wu 001 (IEEE Trans. Circuits Syst., 2020)

Two-Stage Difference-Based Estimation Method for Timing Skew in TI-ADCs. - Xin Li 099; Christian Vogel 001; Jianhui Wu 001 (ISCAS, 2021)

A Background Correlation-Based Timing Skew Estimation Method for Time-Interleaved ADCs. - Xin Li 099; Jianhui Wu 001; Christian Vogel 001 (IEEE Access, 2021)

Hierarchical parallel difference-equalization and channels regrouping based estimation of timing skew for time-interleaved ADCs. - He Zhi; Xin Li 099; Jiayan Yan; Lizhen Zhang; Chun Yang; Jianhui Wu 001 (Microelectron. J., 2022)

A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM. - Yongliang Zhou; Zhen Yang; Yiming Wei; Xiao Lin; Saiai Wu; Wenjuan Lu; Chunyu Peng; Xin Li 099; Xiulong Wu (ISCAS, 2024)

A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC. - Xin Li 099; Mengya Gao; Zihua Ren; Kefeng Yu; Wenjuan Lu; Chenghu Dai; Wei Hu; Chunyu Peng; Xiulong Wu (Microelectron. J., 2024)

Corrigendum to "A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC" [145, March 2024, 106124. - Xin Li 099; Mengya Gao; Zihua Ren; Kefeng Yu; Wenjuan Lu; Chenghu Dai; Wei Hu; Chunyu Peng; Xiulong Wu (Microelectron. J., 2024)

A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC. - Zhiting Lin; Runru Yu; Da Huo; Qingchuan Zhu; Miao Long; Yongqi Qin; Yanchun Liu; Lintao Chen; Simin Wang; Ting Wang; Yousheng Xing; Zeshi Wen; et al. (Microelectron. J., 2024)

High energy efficient and configurable CIM macro for image processing. - Chunyu Peng; Shengyuan Yan; Huayi Ding; Yana Wang; Wenjuan Lu; Chenghu Dai; Xin Li 099; Wei Hu; Xiulong Wu (Microelectron. J., 2024)

An 11-bit two-step column-shared ADC based on Flash/SS architecture for CMOS image sensor. - Qiang Zhao 007; Jitao Xu 005; Chunhui Fan; Ziming Wang; Ruitong Hu; Xin Li 099; Zhigang Li; Licai Hao; Chunyu Peng; Zhiting Lin; Xiulong Wu (Microelectron. J., 2024)

A Floating-Point SRAM-based CIM Macro with Asynchronous Normalization and Parallel Sorting Alignment. - Zhiting Lin; Xin Wang; Xiaofeng Song; Dongcheng Wang; Rongtao Li; Shichen Yu; Wenqiang Zhang; Yu Liu 030; Xin Li 099; Xiulong Wu (ISCAS, 2025)

TSCIM: A 28nm Transposed Stochastic CIM Macro for On-Chip Training and Inference. - Yu Liu 030; Yang Lou; Kangkang Mao; Xin Li 099; Chenghu Dai; Xiulong Wu; Zhiting Lin (ISCAS, 2025)

MTJ based temperature compensated beta multiplier Voltage Reference. - Yongliang Zhou; Yingxue Sun; Jingxue Zhong; Chengxing Dai; Weizhe Tan; Chunyu Peng; Xin Li 099; Zhigang Li; Zhiting Lin; Xiulong Wu (ISCAS, 2025)

MTJ based Temperature-Adaptive VCO (TAVCO) for Compensating CP-PLL Frequency Drift. - Yongliang Zhou; Jingxue Zhong; Yingxue Sun; Chengxing Dai; Weizhe Tan; Chunyu Peng; Wenjuan Lu; Xin Li 099; Zhiting Lin; Xiulong Wu (ISCAS, 2025)

A residual pulse broadening interpolation quantization column-level ADC architecture for CMOS image sensors. - Qiang Zhao 007; Ziming Wang; Chunhui Fan; Bin Qiang; Jitao Xu 005; Xin Li 099; Zhigang Li; Licai Hao; Chunyu Peng; Zhiting Lin; Xiulong Wu (Microelectron. J., 2025)

A low-power, area-efficient digital decimation filter with column-shared counter topology for CMOS image sensor. - Qiang Zhao 007; Jianmin Zhang; Shiqi Dang; Bin Qiang; Xiuying Wang 004; Xin Li 099; Zhigang Li; Chunyu Peng; Zhiting Lin; Xiulong Wu (Microelectron. J., 2025)

A High-Performance and High-Robustness Triple-Node-Upset Tolerant Latch Based on Redundant-Node Hardening. - Qiang Zhao 007; Qingyi Liu; Xinyi Zhang; Licai Hao; Xin Li 099; Shengyue Zhang; Chunyu Peng; Zhiting Lin; Xiulong Wu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

8T-SRAM Computing-in-Memory Macro with Bitline Leakage Compensation. - Chunyu Peng; Junbo Chen; Mengyi Zhao; Wenjuan Lu; Zhiting Lin; Licai Hao; Xin Li 099; Chenghu Dai; Xiulong Wu (Circuits Syst. Signal Process., 2025)

A 28-nm 9T1C SRAM-Based CIM Macro With Hierarchical Capacitance Weighting and Two-Step Capacitive Comparison ADCs for CNNs. - Zhiting Lin; Runru Yu; Yunhao Li; Miao Long; Yu Liu 030; Jianxing Zhou; Da Huo; Qingchuan Zhu; Yue Zhao; Lintao Chen; Chunyu Peng; Qiang Zhao 007; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Full-Array Boolean Logic CIM Macro With Self-Recycling 10T-SRAM Cell for AES Systems. - Xin Li 099; Ying Pan; Qian Jin; Lintao Chen; Yang Lou; Baofa Wu; Jiajun Long; Yongliang Zhou; Chunyu Peng; Xiulong Wu; Zhiting Lin (IEEE Trans. Very Large Scale Integr. Syst., 2025)