A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique. - Xin-Ru Lee; Hsie-Chia Chang; Chen-Yi Lee (APCCAS, 2010)

A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. - Po-Tsang Huang; Xin-Ru Lee; Hsie-Chia Chang; Chen-Yi Lee; Wei Hwang (J. Low Power Electron., 2010)

Stochastic decoding for LDPC convolutional codes. - Xin-Ru Lee; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2012)

Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. - Chih-Wen Yang; Xin-Ru Lee; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ISCAS, 2014)

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. - Xin-Ru Lee; Chih-Wen Yang; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (ESSCIRC, 2015)

A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications. - Xin-Ru Lee; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes. - Xin-Ru Lee; Chih-Wen Yang; Chih-Lung Chen; Hsie-Chia Chang; Chen-Yi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2015)