Parallelizing SRAM arrays with customized bit-cell for binary neural networks. - Rui Liu 005; Xiaochen Peng; Xiaoyu Sun 001; Win-San Khwa; Xin Si; Jia-Jing Chen; Jia-Fang Li; Meng-Fan Chang; Shimeng Yu (DAC, 2018)

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. - Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xin Si; En-Yu Yang; Xiaoyu Sun 001; Rui Liu 005; Pai-Yu Chen; Qiang Li 021; Shimeng Yu; Meng-Fan Chang (ISSCC, 2018)

Circuit Design Challenges in Computing-in-Memory for AI Edge Devices. - Xin Si; He Qian; Meng-Fan Chang; Cheng-Xin Xue; Jian-Wei Su; Zhixiao Zhang; Sih-Han Li; Shyh-Shyuan Sheu; Heng-Yuan Lee; Ping-Cheng Chen; Huaqiang Wu (ASICON, 2019)

A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors. - Zhixiao Zhang; Jia-Jing Chen; Xin Si; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Yen-Cheng Chiu; Je-Min Hong; Shyh-Shyuan Sheu; Sih-Han Li; et al. (A-SSCC, 2019)

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. - Xin Si; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; Yen-Cheng Chiu; Wei-Chen Wei; Ssu-Yen Wu; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; et al. (ISSCC, 2019)

Recent Advances in Compute-in-Memory Support for SRAM Using Monolithic 3-D Integration. - Zhixiao Zhang; Xin Si; Srivatsa Srinivasa; Akshay Krishna Ramanathan; Meng-Fan Chang (IEEE Micro, 2019)

A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. - Xin Si; Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Hiroyuki Yamauchi; Qiang Li 021; Meng-Fan Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations. - Yajuan He; Jiubai Zhang; Xiaoqing Wu; Xin Si; Shaowei Zhen; Bo Zhang 027 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Zhixiao Zhang; Syuan-Hao Sie; et al. (ISSCC, 2020)

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Zhixiao Zhang; Hongwu Jiang; et al. (ISSCC, 2020)

14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse. - Jinshan Yue; Zhe Yuan; Xiaoyu Feng; Yifan He 003; Zhixiao Zhang; Xin Si; Ruhui Liu; Meng-Fan Chang; Xueqing Li 002; Huazhong Yang; Yongpan Liu (ISSCC, 2020)

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. - Yen-Cheng Chiu; Zhixiao Zhang; Jia-Jing Chen; Xin Si; Ruhui Liu; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Je-Min Hung; Shyh-Shyuan Sheu; et al. (IEEE J. Solid State Circuits, 2020)

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. - Xin Si; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Qiang Li 021; Meng-Fan Chang; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; et al. (IEEE J. Solid State Circuits, 2020)

MLFlash-CIM: Embedded Multi-Level NOR-Flash Cell based Computing in Memory Architecture for Edge AI Devices. - Sitao Zeng; Yuxin Zhang; Zhiguo Zhu; Zhaolong Qin; Chunmeng Dou; Xin Si; Qiang Li 001 (AICAS, 2021)

Challenge and Trend of SRAM Based Computation-in-Memory Circuits for AI Edge Devices. - Xin Si; Yongliang Zhou; Jun Yang 006; Meng-Fan Chang (ASICON, 2021)

A 9.08 ENOB 10b 400MS/s Subranging SAR ADC with Subsetted CDAC and PDAS in 40nm CMOS. - Qiang Yu; Xiong Zhou; Kefeng Hu; Zijian Huang 004; Haiwen Chen; Xin Si; Jinda Yang; Qiang Li 021 (ESSCIRC, 2021)

A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning. - Yuxin Zhang; Sitao Zeng; Zhiguo Zhu; Zhaolong Qin; Chen Wang 130; Jingjing Li 001; Sanfeng Zhang; Yajuan He; Chunmeng Dou; Xin Si; Meng-Fan Chang; Qiang Li 021 (ISCAS, 2021)

Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices. - Tianzhu Xiong; Yongliang Zhou; Yuyao Kong; Bo Wang 023; An Guo 001; Yufei Wang; Chen Xue; Haiming Hsu; Xin Si; Jun Yang 006 (ISOCC, 2021)

15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization. - Ruiqi Guo; Zhiheng Yue; Xin Si; Te Hu; Hao Li; Limei Tang; Yabing Wang; Leibo Liu; Meng-Fan Chang; Qiang Li 021; Shaojun Wei; Shouyi Yin (ISSCC, 2021)

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Tianlong Pan; Sih-Han Li; Shih-Chieh Chang; et al. (ISSCC, 2021)

Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices. - Yufei Wang; Yongliang Zhou; Bo Wang 023; Tianzhu Xiong; Yuyao Kong; Xin Si (UCET, 2021)

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Yen-Lin Chung; William Shih; et al. (IEEE J. Solid State Circuits, 2021)

Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control. - Linfang Wang; Wang Ye; Chunmeng Dou; Xin Si; Xiaoxin Xu; Jing Liu 035; Dashan Shang; Jianfeng Gao 005; Feng Zhang 014; Yongpan Liu; Meng-Fan Chang; Qi Liu 010 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Quantization Model Based on a Floating-point Computing-in-Memory Architecture. - Xi Chen 107; An Guo 001; Xinbing Xu; Xin Si; Jun Yang 006 (APCCAS, 2022)

A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model. - Zhongyuan Feng; Bo Wang 023; Zhaoyang Zhang; An Guo 001; Xin Si (APCCAS, 2022)

Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network. - Xingchen Li; Bingzhe Wu; Guangyu Sun 003; Zhe Zhang 006; Zhihang Yuan; Runsheng Wang; Ru Huang 001; Dimin Niu; Hongzhong Zheng; Zhichao Lu; Liang Zhao; Meng-Fan Marvin Chang; et al. (HPCA, 2022)

ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations. - An Guo 001; Yongliang Zhou; Bo Wang 023; Tianzhu Xiong; Chen Xue; Yufei Wang; Xin Si; Jun Yang 006 (ISCAS, 2022)

SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation. - Bo Wang 023; Chen Xue; Han Liu; Xiang Li; Anran Yin; Zhongyuan Feng; Yuyao Kong; Tianzhu Xiong; Haiming Hsu; Yongliang Zhou; An Guo 001; Yufei Wang; et al. (ISCAS, 2022)

A Charge-Digital Hybrid Compute-In-Memory Macro with full precision 8-bit Multiply-Accumulation for Edge Computing Devices. - Jinwu Chen; Tianzhu Xiong; Xin Si (MCSoC, 2022)

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Yen-Lin Chung; Jin-Sheng Ren; et al. (IEEE J. Solid State Circuits, 2022)

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse. - Jinshan Yue; Yongpan Liu; Zhe Yuan; Xiaoyu Feng; Yifan He 002; Wenyu Sun; Zhixiao Zhang; Xin Si; Ruhui Liu; Zi Wang; Meng-Fan Chang; Chunmeng Dou; et al. (IEEE J. Solid State Circuits, 2022)

VCCIM: a voltage coupling based computing-in-memory architecture in 28 nm for edge AI applications. - An Guo 001; Chen Xue; Xi Chen 107; Xin Si (CCF Trans. High Perform. Comput., 2022)

A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. - Hao Cai 001; Zhongjian Bian; Yaoru Hou; Yongliang Zhou; Jia-Le Cui; Yanan Guo 004; Xiaoyun Tian; Bo Liu 019; Xin Si; Zhen Wang 019; Jun Yang 006; Weiwei Shan (ISSCC, 2023)

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. - An Guo 001; Xin Si; Xi Chen 107; Fangyuan Dong; Xingyu Pu; Dongqi Li; Yongliang Zhou; Lizheng Ren; Yeyang Xue; Xueshan Dong; Hui Gao; Yiran Zhang; et al. (ISSCC, 2023)

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. - Bo Wang 023; Chen Xue; Zhongyuan Feng; Zhaoyang Zhang; Han Liu; Lizheng Ren; Xiang Li; Anran Yin; Tianzhu Xiong; Yeyang Xue; Shengnan He; Yuyao Kong; et al. (ISSCC, 2023)

Evaluation Model for Current-Domain SRAM-based Computing-in-Memory Circuits. - Yiran Zhang; Bo Wang 023; Jinwu Chen; Xi Chen 107; Xin Si (MCSoC, 2023)

TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization. - Ruiqi Guo; Zhiheng Yue; Xin Si; Hao Li; Te Hu; Limei Tang; Yabing Wang; Hao Sun; Leibo Liu; Meng-Fan Chang; Qiang Li 021; Shaojun Wei; et al. (IEEE J. Solid State Circuits, 2023)

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Tianlong Pan; Chuan-Jia Jhang; Wei-Hsing Huang; et al. (IEEE J. Solid State Circuits, 2023)

Evaluation Platform of Time-Domain Computing-in-Memory Circuits. - Yuyao Kong; Xi Chen 107; Xin Si; Jun Yang 006 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits. - Zhaoyang Zhang; Jinwu Chen; Xi Chen 107; An Guo 001; Bo Wang 023; Tianzhu Xiong; Yuyao Kong; Xingyu Pu; Shengnan He; Xin Si; Jun Yang 006 (Sci. China Inf. Sci., 2023)

A 28nm 128-kb Exponent- and Mantissa-Computation-InMemory Dual-macro for Floating-point and INT CNNs. - An Guo 001; Xueshan Dong; Fangyuan Dong; Dongqi Li; Yiran Zhang; Jingmin Zhang; Yuchen Tang; Yuhui Shi; Xiao Tan; Bo Liu 019; Weiwei Shan; Hao Cai 001; et al. (A-SSCC, 2024)

A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. - Zhaoyang Zhang; Zhichao Liu; Feiran Liu; Yinhai Gao; Yuchen Ma; Yutong Zhang; An Guo 001; Tianzhu Xiong; Jinwu Chen; Xi Chen 107; Bo Wang 023; Yuchen Tang; et al. (CICC, 2024)

FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow. - Bo Liu 019; Qingwen Wei; Yang Zhang 132; Xingyu Xu 008; Zihan Zou; Xinxiang Huang; Xin Si; Hao Cai 001 (DAC, 2024)

Complementary Series-connected STT-MTJ for Time-based Computing-in-Memory. - Rong Zhou; Bo Liu 019; Xin Si; Hao Cai 001 (ISCAS, 2024)

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. - An Guo 001; Xi Chen 107; Fangyuan Dong; Jinwu Chen; Zhihang Yuan; Xing Hu 010; Yuanpeng Zhang; Jingmin Zhang; Yuchen Tang; Zhican Zhang; Gang Chen 023; Dawei Yang; et al. (ISSCC, 2024)

14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS. - Weiwei Shan; Kaize Zhou; Keran Li; Yuxuan Du; Zhuo Chen; Junyi Qian; Haitao Ge; Jun Yang 006; Xin Si (ISSCC, 2024)

ROTA-I/O: Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness. - Zhe Jiang 004; Shuai Zhao 004; Ran Wei; Xin Si; Gang Chen 023; Nan Guan (RTSS, 2024)

Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness. - Zhe Jiang 004; Shuai Zhao 004; Ran Wei; Xin Si; Gang Chen 023; Nan Guan (CoRR, 2024)

An INT8 Charge-Digital Hybrid Compute-In-Memory Macro With CNN-Friendly Shift-Feed Register Design. - Jinwu Chen; Yitong Zhao; Tianzhu Xiong; Xin Si (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture. - Xi Chen 107; Yitong Zhao; An Guo 001; Jinwu Chen; Fangyuan Dong; Zhaoyang Zhang; Tianzhu Xiong; Bo Wang 023; Yuyao Kong; Xin Si (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. - An Guo 001; Chen Xi; Fangyuan Dong; Xingyu Pu; Dongqi Li; Jingmin Zhang; Xueshan Dong; Hui Gao; Yiran Zhang; Bo Wang 023; Jun Yang 006; Xin Si (IEEE J. Solid State Circuits, 2024)

A 28 nm 16-kb Sign-Extension-Less Digital-Compute-in-Memory Macro With Extension-Friendly Compute Units and Accuracy-Adjustable Adder-Tree. - Xin Si; Fangyuan Dong; Shengnan He; Yuhui Shi; Anran Yin; Hui Gao; Xiang Li (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 22-nm 264-GOPS/mm2 6T SRAM and Proportional Current Compute Cell-Based Computing-in-Memory Macro for CNNs. - Feiran Liu; Anran Yin; Chen Xue; Bo Wang 023; Zhongyuan Feng; Han Liu; Xiang Li; Hui Gao; Tianzhu Xiong; Xin Si (IEEE Trans. Very Large Scale Integr. Syst., 2024)

TRIFP-DCIM: A Toggle-Rate-Immune Floating-point Digital Compute-in-Memory Design with Adaptive-Asymmetric Compute-Tree. - Xing Wang; Tianhui Jiao; Shaochen Li; Yuchen Ma; Zhican Zhang; Zhichao Liu; Xi Chen 107; Xin Si (ASP-DAC, 2025)

A 40nm 4Mb High-Reliability STT-MRAM Achieving 18ns Write-Time and 94.9% Wafer-Level-Die-Yield Across -55°C-to-125°C. - Yaoru Hou; Haoran Du; Jiongzhe Su; Yibo Liu; Zhenghan Fang; Jia-Le Cui; Shuyu Wang; Chenxing Liu-Sun; Xuezhao Wu; Zhihua Xiao; Bo Liu 019; Xin Si; et al. (CICC, 2025)

A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs. - Bo Liu 019; Xingyu Xu 008; Yang Zhang 132; Xilong Kang; Qingwen Wei; Zihan Zou; Jun Yang 006; Hao Cai 001; Xin Si (CICC, 2025)

A L0 Framework with Anisotropic Sparsity and Fairness for 3D Denoising. - Jinfeng Qian; Ling Li; Xin Si; Yong Zhao; Jingliang Zhang (ICIC (1), 2025)

H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference. - Cong Li; Yihan Yin; Xintong Wu; Jingchen Zhu; Zhutianya Gao; Dimin Niu; Qiang Wu 012; Xin Si; Yuan Xie 001; Chen Zhang 001; Guangyu Sun 003 (ISCA, 2025)

AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM. - Yuanpeng Zhang; Xing Hu 010; Xi Chen 107; Zhihang Yuan; Cong Li; Jingchen Zhu; Zhao Wang; Chenguang Zhang; Xin Si; Wei Gao; Qiang Wu 012; Runsheng Wang; et al. (ISCA, 2025)

Variation-Adaptive Negative Bitline and Skip Bitline Pre-charge Scheme for Low-Power SRAM. - Lishuo Deng; Changwei Yan; Yiran Zhang; Xin Si; Weiwei Shan (ISCAS, 2025)

Modeling of Less-Significant Group Quantization for Hybrid CIM Architecture. - Shaochen Li; Xi Chen 107; Lingyi Kong; He Wang; Xing Wang; Yi Yang 001; Xin Si (ISCAS, 2025)

14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer. - Xi Chen 107; Shaochen Li; Zhican Zhang; Wentao Zheng; Xiao Tan; Yuchen Tang; Yuhui Shi; Lizheng Ren; Yibo Mai; Feiran Liu; Jinwu Chen; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching. - An Guo 001; Jingmin Zhang; Xingyu Pu; Yi Yang 001; Defa Wu; Yuchen Tang; Yuhui Shi; Yinghai Gao; Zhichao Liu; Bo Wang 023; Tianzhu Xiong; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two's-Complement MAC for CNNs and Transformers. - Xing Wang; Tianhui Jiao; Yi Yang 001; Shaochen Li; Dongqi Li; An Guo 001; Yuhui Shi; Yuchen Tang; Jinwu Chen; Zhican Zhang; Zhichao Liu; Bo Liu 019; et al. (ISSCC, 2025)

Serial Magnetoresistance Accumulation Supported Spiking Neural Network in STT-MRAM. - Xiaoyun Tian; Zhongjian Bian; Bo Liu 019; Xin Si; Hao Cai 001 (NewCAS, 2025)

Joint-Learning: A Robust Segmentation Method for 3D Point Clouds Under Label Noise. - Mengyao Zhang; Jie Zhou; Tingyun Miao; Yong Zhao; Xin Si; Jingliang Zhang (Comput. Animat. Virtual Worlds, 2025)

A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation. - Tianzhu Xiong; Yuyang Ye 001; Xin Si; Jun Yang 006 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. - Zhaoyang Zhang; Yanqi Zhang; Feiran Liu; Zhichao Liu; Yinhai Gao; Yuchen Ma; Yutong Zhang; An Guo 001; Tianzhu Xiong; Jinwu Chen; Xi Chen 107; Bo Wang 023; et al. (IEEE J. Solid State Circuits, 2025)

An On-Chip-Training Keyword-Spotting Chip Using Interleaved Pipeline and Computation-in-Memory Cluster in 28-nm CMOS. - Junyi Qian; Cai Li; Long Chen; Ruidong Li; Tuo Li; Peng Cao 002; Xin Si; Weiwei Shan (IEEE Trans. Very Large Scale Integr. Syst., 2025)

MPN-S: An Algorithm-Hardware Co-Designed Architecture for High-Efficiency Softmax Computation. - Yuchen Ma; Defa Wu; Yucheng Du; Xing Wang; Xin Si; Chao Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2025)