Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization. - Xin-Wei Shih; Chung-Chun Cheng; Yuan-Kai Ho; Yao-Wen Chang (ASP-DAC, 2010)

High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. - Xin-Wei Shih; Hsu-Chieh Lee; Kuan-Hsien Ho; Yao-Wen Chang (ICCAD, 2010)

Clock rescheduling for timing engineering change orders. - Kuan-Hsien Ho; Xin-Wei Shih; Jie-Hong R. Jiang (ASP-DAC, 2012)

Fast Timing-Model Independent Buffered Clock-Tree Synthesis. - Xin-Wei Shih; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Layer minimization in escape routing for staggered-pin-array PCBs. - Yuan-Kai Ho; Xin-Wei Shih; Yao-Wen Chang; Chung-Kuan Cheng (ASP-DAC, 2013)

Symmetrical buffered clock-tree synthesis with supply-voltage alignment. - Xin-Wei Shih; Tzu-Hsuan Hsu; Hsu-Chieh Lee; Yao-Wen Chang; Kai-Yuan Chao (ASP-DAC, 2013)

Buffered clock tree synthesis considering self-heating effects. - Chung-Wei Lin; Tzu-Hsuan Hsu; Xin-Wei Shih; Yao-Wen Chang (ISLPED, 2014)