High-performance scheduling algorithm for partially parallel LDPC decoder. - Cheng-Zhou Zhan; Xin-Yu Shih; An-Yeu Wu (ICASSP, 2008)

An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 µm CMOS Process. - Xin-Yu Shih; Cheng-Zhou Zhan; Cheng-Hung Lin; An-Yeu Wu (IEEE J. Solid State Circuits, 2008)

A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications. - Xin-Yu Shih; Cheng-Zhou Zhan; Cheng-Hung Lin; An-Yeu Wu (ASP-DAC, 2009)

A Triple-mode LDPC Decoder Design for IEEE 802.11n SYSTEM. - Min-An Chao; Jen-Yang Wen; Xin-Yu Shih; An-Yeu Wu (ISCAS, 2009)

A Channel-Adaptive Early Termination strategy for LDPC decoders. - Yu-Hsin Chen; Yi-Ju Chen; Xin-Yu Shih; An-Yeu Wu (SiPS, 2009)

Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders. - Min-An Chao; Xin-Yu Shih; An-Yeu Wu (J. Signal Process. Syst., 2012)

A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS. - Jie-Wei Lai; Chi-Hsueh Wang; Kaipon Kao; Anson Lin; Yi-Hsien Cho; Lan-chou Cho; Meng-Hsiung Hung; Xin-Yu Shih; Che-Min Lin; Sheng-Hong Yan; Yuan-Hung Chung; Paul C. P. Liang; et al. (ISSCC, 2013)

A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter. - Hua Wang 006; Chun-Hsien Peng; Yaopei Chang; Richard Z. Huang; Chih-Wei Chang; Xin-Yu Shih; Chia-Jui Hsu; Paul C. P. Liang; Ali M. Niknejad; George Chien; Chao Long Tsai; H. C. Hwang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

LEGO-based VLSI design and implementation of polar codes encoder architecture with radix-2 processing engines. - Xin-Yu Shih; Po-Chun Huang; Yu-Chun Chen (APCCAS, 2016)

Reconfigurable VLSI design of processing kernel for multiple-radix single-path delay feedback FFT systems. - Xin-Yu Shih; Hong-Ru Chou; Yue-Qu Liu (GCCE, 2016)

High-speed low-area-cost VLSI design of polar codes encoder architecture using radix-k processing engines. - Xin-Yu Shih; Po-Chun Huang; Yu-Chun Chen (GCCE, 2016)

A 2-D grouping FIFO based hardware architecture for supporting 36-mode hybrid-radix FFT design in 3GPP-LTE systems. - Xin-Yu Shih; Hong-Ru Chou (GCCE, 2017)

Cost-efficient hardware design of coarse and fine rotation based FFT twiddle factor generator for 3GPP LTE applications. - Xin-Yu Shih; Yue-Qu Liu (GCCE, 2017)

Reconfigurable hardware design of low-area-cost computing kernel engine for different radixes of single-path delay feedback FFT systems. - Xin-Yu Shih; Hong-Ru Chou (ICCE, 2017)

48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches. - Xin-Yu Shih; Yue-Qu Liu; Hong-Ru Chou (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems. - Xin-Yu Shih; Hong-Ru Chou (ICT Express, 2018)

VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system. - Xin-Yu Shih; Po-Chun Huang; Hong-Ru Chou (Integr., 2018)

VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications. - Xin-Yu Shih; Hong-Ru Chou; Yue-Qu Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements. - Xin-Yu Shih; Hong-Ru Chou; Yue-Qu Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Design and Analysis of Cost-Efficient Ultra-High-Order Matched Filter Architecture Using 4-Phase Calculating Paths for Underwater Applications. - Xin-Yu Shih (ICCE-TW, 2019)

VLSI Architecture of 36-Mode Reconfigurable FFT Hardware Chip with Newly-Developed 2D-FIFO Arrangement Structure. - Xin-Yu Shih (ICSAI, 2019)

Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding. - Xin-Yu Shih; Hong-Ru Chou (Integr., 2019)

Scalable and Reconfigurable Architecture of Modified KD-Tree ML-Classifier with 5-Point Searching. - Xin-Yu Shih; Chen-Yen Song (ICCE-TW, 2022)

Design and Analysis of 7x7 Median Filter with 8-Step Low-Complexity Fast Searching Approach for Undersea Image Processing Applications. - Xin-Yu Shih; Hsiang-En Wu (ICCE-TW, 2022)

Design Methodology of Queue-Based Fast Classification for Sequential Minimal Optimization in SVM ML-Training. - Xin-Yu Shih; Hsiang-En Wu (ICCE-TW, 2022)

A Systematic and Generic Correlation-Based Design Approach for Data Sample Reduction in ML-Training. - Xin-Yu Shih; Ming-Jyun Wu; Hsiang-En Wu (ICCE-TW, 2022)

Reconfigurable Hardware Architecture of Area-Efficient Multimode Successive Cancellation (SC) Decoder. - Xin-Yu Shih; Jui-Hung Tsai; Bing-Xuan Li; Chi-Ping Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Low-Cost Hardware Design of Fast 3D-Sorter Engine for Successive Cancellation List Polar-Decoders in 5G Applications. - Xin-Yu Shih; Lok Hin Samuel Leung; Geng-Hong Li (ICCE-Taiwan, 2023)

Design and Implementation of Decision-Tree (DT) Online Training Hardware Using Divider-Free GI Calculation and Speeding-Up Double-Root Classifier. - Xin-Yu Shih; Yao Chiu; Hsiang-En Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Unified chip hardware architecture of KD-tree mean-based trainer and speeding-up classifier with repeat-point searching for various applications. - Xin-Yu Shih; Chen-Yen Song; Yao-Yu Lu (Integr., 2023)

Design and Implementation of Dual-Mode Support Vector Machine (SVM) Trainer and Classifier Chip Architecture for Human Disease Detection Applications. - Xin-Yu Shih; Hsiang-En Wu; Ming-Xian Cai (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

High-Area-Efficiency Polar Decoder Chip Architecture Reconfiguring SCL-Decoding With Reconfigurable Pipelined Sorter and SCF-Decoding With Non-Uniform 4-Segment CRC. - Xin-Yu Shih; Yu-Chen Lee; Geng-Hong Li; Jia-Han Xie (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Design and Hardware Implementation of Low-Latency 4-Splitting Tree-Structure-Based K-Means Clustering Trainer and Classifier Chip for Detecting Cybersecurity Attacks. - Xin-Yu Shih; Hsi-Cheng Chen; Xin-Liang Hung (IEEE Trans. Circuits Syst. II Express Briefs, 2025)