Routing tree construction under fixed buffer locations. - Jason Cong; Xin Yuan 005 (DAC, 2000)

Technology mapping for k/m-macrocell based FPGAs. - Jason Cong; Hui Huang 001; Xin Yuan 005 (FPGA, 2000)

Multi-level placement for large-scale mixed-size IC designs. - Chin-Chih Chang; Jason Cong; Xin Yuan 005 (ASP-DAC, 2003)

Multilevel global placement with retiming. - Jason Cong; Xin Yuan 005 (DAC, 2003)

Large-Scale Circuit Placement: Gap and Promise. - Jason Cong; Tim Kong; Joseph R. Shinnerl; Min Xie 004; Xin Yuan 005 (ICCAD, 2003)

Multilevel global placement with congestion control. - Chin-Chih Chang; Jason Cong; David Zhigang Pan; Xin Yuan 005 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Technology mapping and architecture evalution for k/m-macrocell-based FPGAs. - Jason Cong; Hui Huang 001; Xin Yuan 005 (ACM Trans. Design Autom. Electr. Syst., 2005)

Large-scale circuit placement. - Jason Cong; Joseph R. Shinnerl; Min Xie 004; Tim Kong; Xin Yuan 005 (ACM Trans. Design Autom. Electr. Syst., 2005)