Xin Zhang
Orcid: 0000-0002-0579-2268Affiliations:
- University of Tokyo, Institute of Industrial Science, Japan
- IBM T. J. Watson Research Center, Yorktown Heights, NY, USA (since 2014)
- Agency for Science, Technology and Research (A*STAR), Institute of Microelectronics, Singapore (2013)
- University of California, Berkeley, CA, USA (2012)
- Peking University, Beijing (PhD 2008)
According to our database1,
Xin Zhang
authored at least 32 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
ACM Trans. Design Autom. Electr. Syst., March, 2023
A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer.
IEEE J. Solid State Circuits, 2023
2022
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.
IEEE J. Solid State Circuits, 2022
2021
Guest Editorial Cross-Layer Designs, Methodologies, and Systems to Enable Micro AI for On-Device Intelligence.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
From Specification to Topology: Automatic Power Converter Design via Reinforcement Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
2015
An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
2014
IEEE J. Solid State Circuits, 2014
30.7 A 60Mb/s wideband BCC transceiver with 150pJ/b RX and 31pJ/b TX for emerging wearable applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2012
A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection.
IEEE J. Solid State Circuits, 2012
Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and V<sub>TH</sub>-Tuned Oscillator With Fixed Charge Programming.
IEEE J. Solid State Circuits, 2012
A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW.
Proceedings of the Symposium on VLSI Circuits, 2012
A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage.
IEICE Trans. Electron., 2011
0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS.
IEICE Trans. Electron., 2011
0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications.
IEICE Trans. Electron., 2011
A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 80-mV input, fast startup dual-mode boost converter with charge-pumped pulse generator for energy harvesting.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010