0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS. - Po-Hung Chen; Koichi Ishida; Xin Zhang 025; Yasuaki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (CICC, 2010)

0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS. - Yasuyuki Okuma; Koichi Ishida; Yoshikatsu Ryu; Xin Zhang 025; Po-Hung Chen; Kazunori Watanabe; Makoto Takamiya; Takayasu Sakurai (CICC, 2010)

Misleading energy and performance claims in sub/near threshold digital systems. - Yu Pu; Xin Zhang 025; Jim Huang; Atsushi Muramatsu; Masahiro Nomura; Koji Hirairi; Hidehiro Takata; Taro Sakurabayashi; Shinji Miyano; Makoto Takamiya; Takayasu Sakurai (ICCAD, 2010)

An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS. - Xin Zhang 025; Koichi Ishida; Makoto Takamiya; Takayasu Sakurai (ASP-DAC, 2011)

A 80-mV input, fast startup dual-mode boost converter with charge-pumped pulse generator for energy harvesting. - Po-Hung Chen; Koichi Ishida; Xin Zhang 025; Yasuyuki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (A-SSCC, 2011)

A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme. - Po-Hung Chen; Koichi Ishida; Katsuyuki Ikeuchi; Xin Zhang 025; Kentaro Honda; Yasuyuki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (ISSCC, 2011)

0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications. - Po-Hung Chen; Koichi Ishida; Xin Zhang 025; Yasuyuki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2011)

0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS. - Yasuyuki Okuma; Koichi Ishida; Yoshikatsu Ryu; Xin Zhang 025; Po-Hung Chen; Kazunori Watanabe; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2011)

A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage. - Xin Zhang 025; Yu Pu; Koichi Ishida; Yoshikatsu Ryu; Yasuyuki Okuma; Po-Hung Chen; Takayasu Sakurai; Makoto Takamiya (IEICE Trans. Electron., 2011)

Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits. - Yu Pu; Xin Zhang 025; Katsuyuki Ikeuchi; Atsushi Muramatsu; Atsushi Kawasumi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester. - Po-Hung Chen; Koichi Ishida; Xin Zhang 025; Yasuyuki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (ASP-DAC, 2012)

A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW. - Xin Zhang 025; Po-Hung Chen; Yoshikatsu Ryu; Koichi Ishida; Yasuyuki Okuma; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya (VLSIC, 2012)

Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and VTH-Tuned Oscillator With Fixed Charge Programming. - Po-Hung Chen; Koichi Ishida; Katsuyuki Ikeuchi; Xin Zhang 025; Kentaro Honda; Yasuyuki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2012)

An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection. - Po-Hung Chen; Xin Zhang 025; Koichi Ishida; Yasuyuki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2012)

A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation. - Xin Zhang 025; Yu Pu; Koichi Ishida; Yoshikatsu Ryu; Yasuyuki Okuma; Po-Hung Chen; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS. - Xin Zhang 025; Koichi Ishida; Hiroshi Fuketa; Makoto Takamiya; Takayasu Sakurai (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS. - Xin Zhang 025; Po-Hung Chen; Yoshikatsu Ryu; Koichi Ishida; Yasuyuki Okuma; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya (ASP-DAC, 2013)

30.7 A 60Mb/s wideband BCC transceiver with 150pJ/b RX and 31pJ/b TX for emerging wearable applications. - Junghyup Lee; Vishal Vinayak Kulkarni; Ho Chee Keong; Jia Hao Cheong; Peng Li; Jun Zhou 017; Wei-Da Toh; Xin Zhang 025; Yuan Gao 011; Kuang-Wei Cheng; Xin Liu 015; Minkyu Je (ISSCC, 2014)

A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS. - Xin Zhang 025; Po-Hung Chen; Yasuyuki Okuma; Koichi Ishida; Yoshikatsu Ryu; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya (IEEE J. Solid State Circuits, 2014)

Energy harvesting techniques: Energy sources, power management and conversion. - Philex Ming-Yan Fan; Oi-Ying Wong; Ming-Jie Chung; Tze-Yun Su; Xin Zhang 025; Po-Hung Chen (ECCTD, 2015)

An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing. - Xin Liu 015; Jun Zhou 017; Chao Wang 016; Kah-Hyong Chang; Jianwen Luo; Jingjing Lan; Lei Liao; Yat-Hei Lam; Yongkui Yang; Bo Wang 020; Xin Zhang 025; Wang Ling Goh; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage. - Jun Zhou 017; Chao Wang 016; Xin Liu 015; Xin Zhang 025; Minkyu Je (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Research From the IEEE IBM AI Compute and Emerging Technology Symposia. - Matthew M. Ziegler; Krishnan Kailas; Xin Zhang 025; Rajiv V. Joshi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

Non-isolated 48V-to-1V Heterogeneous Integrated Voltage Converters for High Performance Computing in Data Centers. - Minxiang Gong; Xin Zhang 025; Arijit Raychowdhury (MWSCAS, 2020)

From Specification to Topology: Automatic Power Converter Design via Reinforcement Learning. - Shaoze Fan; Ningyuan Cao; Shun Zhang; Jing Li 025; Xiaoxiao Guo; Xin Zhang 025 (ICCAD, 2021)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. - Ankur Agrawal; Sae Kyu Lee; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matt Cohen; Silvia M. Mueller; Jinwook Oh; et al. (ISSCC, 2021)

A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference. - Arnab Neelim Mazumder; Jian Meng; Hasib-Al Rashid; Utteja Kallakuri; Xin Zhang 025; Jae-Sun Seo; Tinoosh Mohsenin (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Guest Editorial Cross-Layer Designs, Methodologies, and Systems to Enable Micro AI for On-Device Intelligence. - Tinoosh Mohsenin; Inna Partin-Vaisband; Houman Homayoun; Jae-Sun Seo; Xin Zhang 025 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

A 181µW Real-Time 3-D Hand-Gesture Recognition System for Edge Applications. - Yuncheng Lu; Zehao Li; Xin Zhang 025; Tony Tae-Hyoung Kim (AICAS, 2022)

A Low-Power Gesture Recognition System utilizing Hybrid Tiny Classifiers. - Yuncheng Lu; Zehao Li; Xin Zhang 025; Tony Tae-Hyoung Kim (ISOCC, 2022)

A 90.4% Peak Efficiency 48V/1V Three-Level Hybrid Dickson Converter with Gradient Descent Run-Time Optimizer and GaN/Si Hybrid Conversion. - Minxiang Gong; Xin Zhang 025; Arijit Raychowdhury (VLSI Technology and Circuits, 2022)

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. - Sae Kyu Lee; Ankur Agrawal; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matthew Cohen; Silvia M. Mueller; Jinwook Oh; et al. (IEEE J. Solid State Circuits, 2022)

SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor with Computing-In-Memory and Dead Neuron Pruning. - Yuncheng Lu; Xin Zhang 025; Zehao Li; Bo Wang 020; Tony Tae-Hyoung Kim (A-SSCC, 2023)

A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SRAM-Based Digital Compute-in-Memory Macro for Accelerating CNNs. - Xin Zhang 025; Vishal Sharma 004; Yuncheng Lu; Yong-Jun Jo; Tony Tae-Hyoung Kim (A-SSCC, 2023)

A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking. - Xi Chen 099; Aly Shoukry; Tianyu Jia; Xin Zhang 025; Raveesh Magod; Nachiket V. Desai; Jie Gu 001 (CICC, 2023)

93.89% Peak Efficiency 24V-to-1V DC-DC Converter with Fast In-Situ Efficiency Tracking and Power-FET Code Roaming. - Zhaoqing Wang; Mao Li; Suhwan Kim 002; Nachiket V. Desai; Ram K. Krishnamurthy; Orlando Lazaro; Andres A. Blanco; Xin Zhang 025; Mingoo Seok (ESSCIRC, 2023)

A Single-Inductor 4-Phase Hybrid Switched-Capacitor Topology for Integrated 48V-to-1V DC-DC Converters. - Muhammad Rizwan Khan; Kang Wei; Xin Zhang 025; Cheng Huang 004 (ISCAS, 2023)

A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS. - Ankur Agrawal; Monodeep Kar; Kyu-Hyoun Kim; Sergey V. Rylov; Jinwook Jung; Seiji Munetoh; Kohji Hosokawa; Xin Zhang 025; Bahman Hekmatshoartabari; Fabio Carta; Martin Cochet; Robert Casatuta; et al. (VLSI Technology and Circuits, 2023)

Proactive Power Regulation with Real-time Prediction and Fast Response Guardband for Fine-grained Dynamic Voltage Droop Mitigation on Digital SoCs. - Xi Chen 099; Jiaxiang Feng; Aly Shoukry; Xin Zhang 025; Raveesh Magod; Nachiket V. Desai; Jie Gu 001 (VLSI Technology and Circuits, 2023)

A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer. - Minxiang Gong; Hua Chen; Xin Zhang 025; Rinkle Jain; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2023)

Power Converter Circuit Design Automation Using Parallel Monte Carlo Tree Search. - Shaoze Fan; Shun Zhang; Jianbo Liu; Ningyuan Cao; Xiaoxiao Guo; Jing Li 025; Xin Zhang 025 (ACM Trans. Design Autom. Electr. Syst., 2023)

A Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration. - Xin Zhang 025; Yuncheng Lu; Bo Wang 020; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks. - Maitreyi Ashok; Saurav Maji; Xin Zhang 025; John Cohn; Anantha P. Chandrakasan (CICC, 2024)

A Monolithic 3-Level Single-Inductor Multiple-Output Buck Converter with State-Based Non-Linear Control Capable of Handling 1A/1.5ns Transient with On-Die LC. - Junyao Tang; Jianqiang Jiang; Lei Zhao; Xin Zhang 025; Kang Wei; Cheng Huang 004 (CICC, 2024)

Graph-Transformer-based Surrogate Model for Accelerated Converter Circuit Topology Design. - Shaoze Fan; Haoshu Lu; Shun Zhang; Ningyuan Cao; Xin Zhang 025; Jing Li 025 (DAC, 2024)

LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits. - Chen-Chia Chang; Yikang Shen; Shaoze Fan; Jing Li 025; Shun Zhang; Ningyuan Cao; Yiran Chen 001; Xin Zhang 025 (ICML, 2024)

A 24/48V to 0.8V-1.2V All-Digital Synchronous Buck Converter with Package-Integrated GaN power FETs and 180nm Silicon Controller IC. - Kaushik Bhattacharyya; Minxiang Gong; Muya Chang; Xin Zhang 025; Arijit Raychowdhury (ISCAS, 2024)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits. - Chen-Chia Chang; Yikang Shan; Shaoze Fan; Jing Li 073; Shun Zhang; Ningyuan Cao; Yiran Chen 001; Xin Zhang 025 (CoRR, 2024)

A Ten-Level Series-Capacitor 24-to-1-V DC-DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail. - Zhaoqing Wang; Mao Li; Suhwan Kim 002; Nachiket V. Desai; Ram K. Krishnamurthy; Xin Zhang 025; Mingoo Seok (IEEE J. Solid State Circuits, 2024)

A 96.1% Efficiency Single-Inductor Multiple-Output (SIMO) Buck Converter With 2.1-A/ns Transient Speed and 2.2-A Maximum Current Capacity. - Lei Zhao; Junyao Tang; Xin Zhang 025; Kang Wei; Raveesh Magod; Cheng Huang 004 (IEEE J. Solid State Circuits, 2024)

A 93.9% Peak Efficiency 3V-to-40V-Input GaN-based DC-DC Converter with Unified Reliability and Efficiency Adaptive Control. - Zhaoqing Wang; Yichen Xu; Suhwan Kim 002; Nachiket V. Desai; Minxiang Gong; Ram Krishnamuthy; Xin Zhang 025; Mingoo Seok (CICC, 2025)

Efficient Circuit Performance Prediction Using Machine Learning: From Schematic to Layout and Silicon Measurement with Minimal Data Input. - Dimple Vijay Kochar; Maitreyi Ashok; John Cohn; Anantha P. Chandrakasan; Xin Zhang 025 (ISCAS, 2025)

A 14-nm Energy-Efficient and Reconfigurable Analog Current-Domain In-Memory Compute SRAM Accelerator. - Aya G. Amer; Maitreyi Ashok; Xin Zhang 025; John Cohn; Anantha P. Chandrakasan (VLSID, 2025)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)

SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor for IoT Devices. - Yuncheng Lu; Xin Zhang 025; Bo Wang 020; Tony Tae-Hyoung Kim (IEEE J. Solid State Circuits, 2025)

LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation. - Chen-Chia Chang; Wan-Hsuan Lin; Yikang Shen; Yiran Chen 001; Xin Zhang 025 (CoRR, 2025)

A 65-nm Proactive Power Management Technique With Real-Time Machine Learning Engine for Droop Prediction and Mitigation on Microprocessors. - Xi Chen 099; Jiaxiang Feng; Aly Shoukry; Xin Zhang 025; Raveesh Magod; Nachiket V. Desai; Jie Gu 001 (IEEE J. Solid State Circuits, 2025)

Digital In-Memory Compute for Machine Learning Applications With Input and Model Security. - Maitreyi Ashok; Saurav Maji; Xin Zhang 025; John Cohn; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2025)