An Efficient Computation of Statistically Critical Sequential Paths Under Retiming. - Mongkol Ekpanyapong; Xin Zhao 001; Sung Kyu Lim (ASP-DAC, 2007)

Buffered clock tree synthesis for 3D ICs under thermal variations. - Jacob R. Minz; Xin Zhao 001; Sung Kyu Lim (ASP-DAC, 2008)

Pre-bond testable low-power clock tree design for 3D stacked ICs. - Xin Zhao 001; Dean L. Lewis; Hsien-Hsin S. Lee; Sung Kyu Lim (ICCAD, 2009)

Slew-aware clock tree design for reliable subthreshold circuits. - Jeremy R. Tolbert; Xin Zhao 001; Sung Kyu Lim; Saibal Mukhopadhyay (ISLPED, 2009)

Buffered clock tree sizing for skew minimization under power and thermal budgets. - Krit Athikulwongse; Xin Zhao 001; Sung Kyu Lim (ASP-DAC, 2010)

Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs. - Xin Zhao 001; Sung Kyu Lim (ASP-DAC, 2010)

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. - Michael B. Healy; Krit Athikulwongse; Rohan Goel; Mohammad M. Hossain; Dae Hyun Kim 004; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Moongon Jung; Brian Ouellette; Mohit Pathak; et al. (CICC, 2010)

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. - Jae-Seok Yang; Jiwoo Pak; Xin Zhao 001; Sung Kyu Lim; David Z. Pan (ASP-DAC, 2011)

Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores. - Dean L. Lewis; Shreepad Panth; Xin Zhao 001; Sung Kyu Lim; Hsien-Hsin S. Lee (ICCD, 2011)

Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits. - Xin Zhao 001; Jeremy R. Tolbert; Chang Liu 034; Saibal Mukhopadhyay; Sung Kyu Lim (ISLPED, 2011)

Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems. - Jeremy R. Tolbert; Xin Zhao 001; Sung Kyu Lim; Saibal Mukhopadhyay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs. - Xin Zhao 001; Dean L. Lewis; Hsien-Hsin S. Lee; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs. - Xin Zhao 001; Sung Kyu Lim (ASP-DAC, 2012)

Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs. - Xin Zhao 001; Michael Scheuermann; Sung Kyu Lim (DAC, 2012)

TSV array utilization in low-power 3D clock network design. - Xin Zhao 001; Sung Kyu Lim (ISLPED, 2012)

3D-MAPS: 3D Massively parallel processor with stacked memory. - Dae Hyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (ISSCC, 2012)

Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits. - Xin Zhao 001; Jeremy R. Tolbert; Saibal Mukhopadhyay; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Reliable clock and power delivery network design for three-dimensional integrated circuits. - Xin Zhao 001 (2012)

Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model. - Yang Shang; Chun Zhang; Hao Yu 001; Chuan Seng Tan; Xin Zhao 001; Sung Kyu Lim (ASP-DAC, 2013)

Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs. - Xin Zhao 001; Yang Wan; Michael Scheuermann; Sung Kyu Lim (ICCAD, 2013)

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). - Daehyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (IEEE Trans. Computers, 2015)